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XeBuZer0

Contador de 4 bits

Jan 18th, 2023
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VHDL 0.42 KB | Source Code | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use IEEE.std_logic_unsigned.all;
  4.  
  5. entity contador is port(
  6. clk,sentido:    in std_logic;
  7. conta:buffer std_logic_vector(3 downto 0)
  8. );
  9. end contador;
  10.  
  11. architecture archicontador of contador is
  12. begin
  13. process (clk)
  14. begin
  15.     if(clk'event and clk='1') then
  16.     if sentido = '1' then
  17.         conta <= conta - 1;
  18.     else
  19.         conta <= conta + 1;
  20.     end if;
  21.     end if;
  22. end process;
  23. end archicontador;
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