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-- Company:
-- Engineer:
--
-- Create Date:   10:56:14 03/19/2019
-- Design Name:
-- Module Name:   /home/adam/ISE/projekty/lcdddd/stoper/test.vhd
-- Project Name:  stoper
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: stoper
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test IS
END test;

ARCHITECTURE behavior OF test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT stoper
    PORT(
         clk_i : IN  std_logic;
         led7_an_o : OUT  std_logic_vector(3 downto 0);
         led7_seg_o : OUT  std_logic_vector(7 downto 0);
         start_stop_button_i : IN  std_logic;
         rst_i : IN  std_logic
        );
    END COMPONENT;


   --Inputs
   signal clk_i : std_logic := '0';
   signal start_stop_button_i : std_logic := '0';
   signal rst_i : std_logic := '0';

    --Outputs
   signal led7_an_o : std_logic_vector(3 downto 0);
   signal led7_seg_o : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_i_period : time := 20ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: stoper PORT MAP (
          clk_i => clk_i,
          led7_an_o => led7_an_o,
          led7_seg_o => led7_seg_o,
          start_stop_button_i => start_stop_button_i,
          rst_i => rst_i
        );

   -- Clock process definitions
   clk_i_process :process
   begin
        clk_i <= '0';
        wait for clk_i_period/2;
        clk_i <= '1';
        wait for clk_i_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100ms.
      wait for 100ns;
            start_stop_button_i <= '1';
            wait for 200ns;
            start_stop_button_i <= '0';
        wait for 100ns;
            start_stop_button_i <= '1';
            wait for 2500ns;
            start_stop_button_i <= '0';
            wait for 1000ns;
            start_stop_button_i <= '1';
            wait for 2500ns;
            start_stop_button_i <= '0';
            wait for 1000ns;
            start_stop_button_i <= '1';
            wait for 2500ns;
            start_stop_button_i <= '0';
            wait for 1000ns;
            start_stop_button_i <= '1';
            wait for 2500ns;
            start_stop_button_i <= '0';

      wait for clk_i_period*1000000000;

      -- insert stimulus here

      wait;
   end process;

END;