JayBawankar

dcfm dataflow and

Jul 23rd, 2017
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VHDL 0.13 KB | None | 0 0
  1. entity and1 is
  2. port(x2,y2:in bit; c:out bit);
  3. end and1;
  4. architecture dataflow of and1 is
  5. begin
  6. c<=x2 and y2;
  7. end dataflow;
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