--Francesco Cervellera [francesco.cervellera@gmail.com (+39)3346169924]
--SX2 Register Byte Reader

library ieee;
use ieee.std_logic_1164.all;

entity SX2RegisterByteReader is

    port(
    --Sync port
        CLK      : in   std_logic; --Clock for the FSM
        RESET    : in   std_logic; --Async Reset

    --In port
        READREQ  : in   std_logic; --REQUEST a read from a register of SX2. The FSM will take WORKING active untill the process is running.
        READLAST : in   std_logic; --put in output the last readed byte from the register

        ADDR     : in   std_logic_vector(5 downto 0); --The Register Address from which FSM will read

    --Out port
        OUTLAST  : out  std_logic; --Rised when the last requested data is held by the fsm
        DATA     : out  std_logic_vector(7 downto 0); --The Data That FSM will READ

        WORKING  : out  std_logic; --This signal is actived when the FSM is running

        USB_READY   : in std_logic;  --Ref SX2 datasheet
        USB_FIFOADR : out std_logic_vector(2 downto 0); --Nedded to choice the command functionality

        CMDW_DATA   : out std_logic_vector(7 downto 0); --Data read from the SX2CommandReader
        CMDW_WREQ   : out std_logic; --Signal
        CMDW_WRITING: in std_logic;

        CMDR_DATA   : in std_logic_vector(7 downto 0); --Data read from the SX2CommandReader
        CMDR_DATATYPE: in std_logic; --Data type read;
        CMDR_RLREQ  : out std_logic;
        CMDR_RREQ   : out std_logic; --Signal
        CMDR_OUTL   : in std_logic;
        CMDR_READING: in std_logic
    );

end entity;

architecture rtl of SX2RegisterByteReader is

    type state_type is (s_IDLE, s_SETCMD, s_WRITEADR, s_WAITADR, s_READREQ, s_WAITREADREQ, s_READ, s_STOREDATA, s_OUTLAST);
    signal state    : state_type;
    signal QRunning : std_logic;

    signal QOutLast : std_logic;
    signal QReadRequest : std_logic;
    signal QReadLastRequest : std_logic;
    signal QDataReadOUT : std_logic_vector(7 downto 0);

    signal QWriteRequest : std_logic;
    signal QDataWriteOUT    : std_logic_vector(7 downto 0);

begin

    -- Logic to advance to the next state
    process (CLK, RESET)

    begin
        if RESET = '0' then
            state <= s_IDLE;
        elsif (rising_edge(CLK)) then
            case state is
                when s_IDLE=>
                --Wait until the external logic dosen't request for a write
                    if READREQ = '1' then
                        state <= s_SETCMD;
                    elsif READLAST = '1' then
                        state <= s_OUTLAST;
                    else
                        state <= s_IDLE;
                    end if;
                when s_OUTLAST =>
                    if READLAST = '0' then
                        state <= s_IDLE;
                    else
                        state <= s_OUTLAST;
                    end if;
                when s_SETCMD=>
                --Set USB_FIFOADR to [100] and wait for the ack from the SX2
                    if USB_READY = '1' then
                        state <= s_WRITEADR;
                    else
                        state <= s_SETCMD;
                    end if;
                when s_WRITEADR=>
                --Write register's address using SX2CmdXXXXWrite
                    state <= s_WAITADR;
                when s_WAITADR =>
                --Wait until SX2CmdXXXXWrite finish the write sequence
                    if CMDW_WRITING = '0' then
                        state <= s_READREQ;
                    else
                        state <= s_WAITADR;
                    end if;
                when s_READREQ =>
                --Post a request of read to SX2CmdXXXXRead
                    state <= s_WAITREADREQ;
                when s_WAITREADREQ =>
                --Wait until SX2CmdXXXXRead finish the read sequence
                    if CMDR_READING = '0' then
                        state <= s_READ;
                    else
                        state <= s_WAITREADREQ;
                    end if;
                when s_READ =>
                --Read the last read byte from SX2CmdXXXXRead
                    if CMDR_OUTL = '1' then
                        if CMDR_DATATYPE = '1' then
                            state <= s_STOREDATA;
                        else
                            state <= s_WRITEADR;
                        --!!!!!!!!!!!!!!ATTENZIONE !!!!!!!!!!!!!!!
                        --PERDITA DATI INTERRUPT
                        end if;
                    else
                        state <= s_READ;
                    end if;
                when s_STOREDATA =>
                --Store the data read into internal register
                    state <= s_IDLE;
            end case;
        end if;
    end process;

    -- Output depends solely on the current state
    process (state)
    variable QAddrIn : std_logic_vector(5 downto 0);
    variable QData   : std_logic_vector(7 downto 0);
    begin
        case state is
            when s_IDLE =>
                --Set this flag to 0
                QRunning <= '0';
                QOutLast <= '0';
                QDataWriteOUT <= (others => 'X');

                QWriteRequest <= 'X';
                QReadRequest <= 'X';
            when s_OUTLAST =>
                QRunning <= '0';
                QOutLast <= '1';

                QDataReadOUT <= QData;

                QWriteRequest <= 'X';
                QReadRequest <= 'X';
            when s_SETCMD =>
                QRunning <= '1';
                QOutLast <= '0';
                --Record The Addr to be used
                QAddrIn := ADDR;
                QDataWriteOUT <= (others => 'X');
                QWriteRequest <= '0';
                QReadRequest <= '0';
            when s_WRITEADR =>
                QRunning <= '1';
                QOutLast <= '0';
                --Query for read the QAddrIn
                QDataWriteOUT(7) <= '1';
                QDataWriteOUT(6) <= '1';
                QDataWriteOUT(5 downto 0) <= QAddrIn;
                QReadRequest <= '0';
                QWriteRequest <= '1'; --Submit the request to the SX2CmdXXXXWrite
            when s_WAITADR =>
                QRunning <= '1';
                QOutLast <= '0';
                --Query for read the QAddrIn
                QDataWriteOUT(7) <= '1';
                QDataWriteOUT(6) <= '1';
                QDataWriteOUT(5 downto 0) <= QAddrIn;
                QReadRequest <= '0';
                QWriteRequest <= '0';
            when s_READREQ =>
                QRunning <= '1';
                QOutLast <= '0';
                QDataWriteOUT <= (others => 'Z');
                QReadRequest <= '1';
                QWriteRequest <= '0';
            when s_WAITREADREQ =>
                QRunning <= '1';
                QOutLast <= '0';
                QDataWriteOUT <= (others => 'Z');
                QReadRequest <= '0';
                QWriteRequest <= '0';
            when s_READ =>
                QRunning <= '1';
                QOutLast <= '0';
                CMDR_RLREQ <= '1';
                QDataWriteOUT <= (others => 'Z');
                QReadRequest <= '0';
                QWriteRequest <= '0';
            when s_STOREDATA =>
                QRunning <= '1';
                QOutLast <= '0';
                CMDR_RLREQ <= '0';
                QData := CMDR_DATA;
                QReadRequest <= '0';
                QWriteRequest <= '0';
        end case;
    end process;



    --TriState Port !
    DATA <= (others => 'Z') when (QOutLast = '0') else QDataReadOUT;
    OUTLAST <= QOutLast;

    USB_FIFOADR <= (others => 'Z') when (QRunning = '0') else "100";
    CMDW_DATA <= (others => 'Z') when (QRunning = '0') else QDataWriteOUT;
    CMDW_WREQ <= 'Z' when (QRunning = '0') else QWriteRequest;
    CMDR_RREQ <= 'Z' when (QRunning = '0') else QReadRequest;
    WORKING <= QRunning;
end rtl;