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--
--                                      CounterUpDown
--
--                                Grzegorz Radomski
--
--                     Data rozpoczecia projektu:
--                     Data ostatniej modyfikacji:
--
----------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

--use work.Types.all;


----------------------------------------------------------------------------------------
--  Deklaracja interfejsu kontrolera ARCP dla 1 fazy (galezi falownika)

-- use work.Types.all;


entity MemoryChip is

 port(Clock : in std_logic;       -- sygnal zegarowy
 Reset      : in std_logic;       -- sygnal zerujacy
 CS         : in std_logic;       -- sygnal wyboru ukladu
 WR, RD : in std_logic;
 Data : inout std_logic_vector(15 downto 0); -- sygnaly pelny pusty
 Address : in integer range 0 to 15);
end MemoryChip;

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architecture behavior of MemoryChip is

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--
begin
--  opis dzialania

----------------------------------------------------------------------------------------
-- Sterownik PWM

Mem_system: process

 type TMem is array(0 to 16) of std_logic_vector(15 downto 0);
 variable Count       : std_logic_vector (15 downto 0); -- licznik
 variable DataB       : std_logic_vector (15 downto 0); -- bufor
 variable Mem : TMem;
begin
 wait until Clock='1';


DataB:="ZZZZZZZZZZZZZZZZ";
 if (Reset='0') then



 else -- Reset

-------------------------------------------------------------------------------------------------------------------

  -- Dekoder wyboru do zapisu/odczytu
  if (CS='0') then
   if (RD='0') then DataB := Mem(Address); end if;
   if (WR='0') then Mem(Address) := Data; end if;
  end if; -- ((CS='0')


 end if; -- Reset

  Data <= DataB;

end process Mem_system;
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end behavior;

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