irq

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 * Copyright (C) 2010 John Crispin <john@phrozen.org>
 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 */

#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/irqdomain.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/module.h>

#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>

#include <lantiq_soc.h>
#include <irq.h>

/* register definitions - internal irqs */
#define LTQ_ICU_IM0_ISR     0x0000
#define LTQ_ICU_IM0_IER     0x0008
#define LTQ_ICU_IM0_IOSR    0x0010
#define LTQ_ICU_IM0_IRSR    0x0018
#define LTQ_ICU_IM0_IMR     0x0020
#define LTQ_ICU_IM1_ISR     0x0028
#define LTQ_ICU_OFFSET      (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)

/* register definitions - external irqs */
#define LTQ_EIU_EXIN_C      0x0000
#define LTQ_EIU_EXIN_INIC   0x0004
#define LTQ_EIU_EXIN_INC    0x0008
#define LTQ_EIU_EXIN_INEN   0x000C

/* number of external interrupts */
#define MAX_EIU         6

/* the performance counter */
#define LTQ_PERF_IRQ        (INT_NUM_IM4_IRL0 + 31)

/*
 * irqs generated by devices attached to the EBU need to be acked in
 * a special manner
 */
#define LTQ_ICU_EBU_IRQ     22

#define ltq_icu_w32(vpe, m, x, y)   ltq_w32((x), ltq_icu_membase[vpe][m] + (y))
#define ltq_icu_r32(vpe, m, x)      ltq_r32(ltq_icu_membase[vpe][m] + (x))

#define ltq_eiu_w32(x, y)   ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_eiu_r32(x)      ltq_r32(ltq_eiu_membase + (x))

/* our 2 ipi interrupts for VSMP */
#define MIPS_CPU_IPI_RESCHED_IRQ    0
#define MIPS_CPU_IPI_CALL_IRQ       1

/* we have a cascade of 8 irqs */
#define MIPS_CPU_IRQ_CASCADE        8

#define MAX_VPES 2

/*
 * Convenience Macro.  Should be somewhere generic.
 */
#define get_current_vpe()   \
        ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)

#if 0

#ifdef CONFIG_SMP
#define LOCK_VPE() \
        local_irq_save(flags); \
        mtflags = dmt()

#define UNLOCK_VPE() \
        emt(mtflags); \
        local_irq_restore(flags)

#define LOCK_CORE() \
        local_irq_save(flags); \
        mtflags = dvpe()

#define UNLOCK_CORE() \
        evpe(mtflags); \
        local_irq_restore(flags)
#else /* CONFIG_SMP*/
#define LOCK_VPE()
#define UNLOCK_VPE()
#endif /* CONFIG_SMP */

#else
#define LOCK_VPE()      (void)flags;(void)mtflags
#define UNLOCK_VPE()
#define LOCK_CORE()     (void)flags;(void)mtflags
#define UNLOCK_CORE()
#endif

static int exin_avail;
static u32 ltq_eiu_irq[MAX_EIU];
static void __iomem *ltq_icu_membase[MAX_VPES][MAX_IM];
static void __iomem *ltq_eiu_membase;
static struct irq_domain *ltq_domain;
static DEFINE_SPINLOCK(ltq_eiu_lock);
static int ltq_perfcount_irq;

int ltq_eiu_get_irq(int exin)
{
    if (exin < exin_avail)
        return ltq_eiu_irq[exin];
    return -1;
}

void ltq_disable_irq(struct irq_data *d)
{
    u32 ier = LTQ_ICU_IM0_IER;
    int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
    int im = offset / INT_NUM_IM_OFFSET;
        int vpe = get_current_vpe();
#ifdef CONFIG_SMP
        unsigned long flags, mtflags;
#endif
        offset %= INT_NUM_IM_OFFSET;
        LOCK_VPE();
    ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, ier) & ~BIT(offset), ier);
        UNLOCK_VPE();
}

void ltq_mask_and_ack_irq(struct irq_data *d)
{
    u32 ier = LTQ_ICU_IM0_IER;
    u32 isr = LTQ_ICU_IM0_ISR;
    int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
    int im = offset / INT_NUM_IM_OFFSET;
        int vpe = get_current_vpe();
#ifdef CONFIG_SMP
        unsigned long flags, mtflags;
#endif

    offset %= INT_NUM_IM_OFFSET;
        LOCK_VPE();
    ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, ier) & ~BIT(offset), ier);
    ltq_icu_w32(vpe, im, BIT(offset), isr);
        UNLOCK_VPE();
}
EXPORT_SYMBOL(ltq_mask_and_ack_irq);

static void ltq_ack_irq(struct irq_data *d)
{
    u32 isr = LTQ_ICU_IM0_ISR;
    int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
    int im = offset / INT_NUM_IM_OFFSET;
        int vpe = get_current_vpe();
#ifdef CONFIG_SMP
        unsigned long flags, mtflags;
#endif

    offset %= INT_NUM_IM_OFFSET;
        LOCK_VPE();
    ltq_icu_w32(vpe, im, BIT(offset), isr);
        UNLOCK_VPE();
}

void ltq_enable_irq(struct irq_data *d)
{
    u32 ier = LTQ_ICU_IM0_IER;
        u32 isr = LTQ_ICU_IM0_ISR;
    int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
    int im = offset / INT_NUM_IM_OFFSET;
        int vpe = get_current_vpe();
#ifdef CONFIG_SMP
        unsigned long flags, mtflags;
#endif

    offset %= INT_NUM_IM_OFFSET;
        LOCK_VPE();
// TODO present in the v3.10 kernel, but system seems to work without, test?
#if 0
    /* Bug fix for dummy interrupt */
        /* if this is a EBU irq, we need to ack it or get a deadlock */
        if ((offset == LTQ_ICU_EBU_IRQ) && (im == 0) && LTQ_EBU_PCC_ISTAT)
                ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
                        LTQ_EBU_PCC_ISTAT);

    /* Bug fix for fake interrupt */
        ltq_icu_w32(vpe, im, BIT(offset), isr);
#else
    (void)isr;(void)im;(void)ier;
#endif

    ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, ier) | BIT(offset), ier);
        UNLOCK_VPE();
}

static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
{
    int i;
    unsigned long flags;

    for (i = 0; i < exin_avail; i++) {
        if (d->hwirq == ltq_eiu_irq[i]) {
            int val = 0;
            int edge = 0;

            switch (type) {
            case IRQF_TRIGGER_NONE:
                break;
            case IRQF_TRIGGER_RISING:
                val = 1;
                edge = 1;
                break;
            case IRQF_TRIGGER_FALLING:
                val = 2;
                edge = 1;
                break;
            case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
                val = 3;
                edge = 1;
                break;
            case IRQF_TRIGGER_HIGH:
                val = 5;
                break;
            case IRQF_TRIGGER_LOW:
                val = 6;
                break;
            default:
                pr_err("invalid type %d for irq %ld\n",
                    type, d->hwirq);
                return -EINVAL;
            }

            if (edge)
                irq_set_handler(d->hwirq, handle_edge_irq);

spin_lock_irqsave(&ltq_eiu_lock, flags);
// TODO this is atomic in v3.10 version
            ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) & (~ (val << (i * 4)))) |
                (val << (i * 4)), LTQ_EIU_EXIN_C);
spin_unlock_irqrestore(&ltq_eiu_lock, flags);


        }
    }

    return 0;
}

static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
{
    int i;

    ltq_enable_irq(d);
    for (i = 0; i < exin_avail; i++) {
        if (d->hwirq == ltq_eiu_irq[i]) {
            /* by default we are low level triggered */
            ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
            /* clear all pending */
            ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
                LTQ_EIU_EXIN_INC);
            /* enable */
            ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
                LTQ_EIU_EXIN_INEN);
            break;
        }
    }

    return 0;
}

static void ltq_shutdown_eiu_irq(struct irq_data *d)
{
    int i;

    ltq_disable_irq(d);
    for (i = 0; i < exin_avail; i++) {
        if (d->hwirq == ltq_eiu_irq[i]) {
            /* disable */
            ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
                LTQ_EIU_EXIN_INEN);
            break;
        }
    }
}

#ifdef CONFIG_MIPS_MT_SMP
static int ltq_icu_irq_set_affinity(struct irq_data *d,
                                    const struct cpumask *cpumask, bool force)
{
        int cpu;
        unsigned long flags;
        unsigned int  mtflags;
        u32 ier = LTQ_ICU_IM0_IER;
        int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
        int im = offset / INT_NUM_IM_OFFSET;

        LOCK_CORE();

    offset %= INT_NUM_IM_OFFSET;

        for_each_online_cpu(cpu) {

//pr_info("  cpu%i t=%i %08x %08x %px\n",cpu,cpumask_test_cpu(cpu, cpumask),im,offset,ltq_icu_membase[cpu][im] + (ier));

#if 1
        if (!cpumask_test_cpu(cpu, cpumask))
            ltq_icu_w32(cpu, im, ltq_icu_r32(cpu, im, ier) & ~BIT(offset), ier);
                else
            ltq_icu_w32(cpu, im, ltq_icu_r32(cpu, im, ier) | BIT(offset), ier);
#else
    (void)im;(void)ier;
#endif
        }

    //v4 kernel requires this, taken from some other SMP board
    irq_data_update_effective_affinity(d, cpumask);

        UNLOCK_CORE();
        return IRQ_SET_MASK_OK;
}
#endif

static struct irq_chip ltq_irq_type = {
    .name = "icu",
    .irq_enable = ltq_enable_irq,
    .irq_disable = ltq_disable_irq,
    .irq_unmask = ltq_enable_irq,
    .irq_ack = ltq_ack_irq,
    .irq_mask = ltq_disable_irq,
    .irq_mask_ack = ltq_mask_and_ack_irq,
#ifdef CONFIG_MIPS_MT_SMP
        .irq_set_affinity = ltq_icu_irq_set_affinity,
#endif
};

static struct irq_chip ltq_eiu_type = {
    .name = "eiu",
    .irq_startup = ltq_startup_eiu_irq,
    .irq_shutdown = ltq_shutdown_eiu_irq,
    .irq_enable = ltq_enable_irq,
    .irq_disable = ltq_disable_irq,
    .irq_unmask = ltq_enable_irq,
    .irq_ack = ltq_ack_irq,
    .irq_mask = ltq_disable_irq,
    .irq_mask_ack = ltq_mask_and_ack_irq,
    .irq_set_type = ltq_eiu_settype,
};

static void ltq_hw_irqdispatch(int module)
{
    u32 irq;
        int vpe = get_current_vpe();
#ifdef CONFIG_SMP
        unsigned long flags, mtflags;
#endif

        LOCK_VPE();
    irq = ltq_icu_r32(vpe, module, LTQ_ICU_IM0_IOSR);
        UNLOCK_VPE();

    if (irq == 0)
        return;

    /*
     * silicon bug causes only the msb set to 1 to be valid. all
     * other bits might be bogus
     */
    irq = __fls(irq);
    do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));

    /* if this is a EBU irq, we need to ack it or get a deadlock */
    if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
        ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
            LTQ_EBU_PCC_ISTAT);
}

#define DEFINE_HWx_IRQDISPATCH(x)                   \
    static void ltq_hw ## x ## _irqdispatch(void)           \
    {                               \
        ltq_hw_irqdispatch(x);                  \
    }
DEFINE_HWx_IRQDISPATCH(0)
DEFINE_HWx_IRQDISPATCH(1)
DEFINE_HWx_IRQDISPATCH(2)
DEFINE_HWx_IRQDISPATCH(3)
DEFINE_HWx_IRQDISPATCH(4)

#if MIPS_CPU_TIMER_IRQ == 7
static void ltq_hw5_irqdispatch(void)
{
    do_IRQ(MIPS_CPU_TIMER_IRQ);
}
#else
DEFINE_HWx_IRQDISPATCH(5)
#endif

static void ltq_hw_irq_handler(struct irq_desc *desc)
{
    ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
}

#ifdef CONFIG_MIPS_MT_SMP
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
    setup_irq(irq, action);
    irq_set_handler(irq, handle_percpu_irq);
}

static void ltq_sw0_irqdispatch(void)
{
    do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ltq_sw1_irqdispatch(void)
{
    do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
    scheduler_ipi();
    return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
    generic_smp_call_function_interrupt();
    return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
    .handler    = ipi_resched_interrupt,
    .flags      = IRQF_PERCPU,
    .name       = "IPI_resched"
};

static struct irqaction irq_call = {
    .handler    = ipi_call_interrupt,
    .flags      = IRQF_PERCPU,
    .name       = "IPI_call"
};
#endif

asmlinkage void plat_irq_dispatch(void)
{
    unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
    int irq;

    if (!pending) {
        spurious_interrupt();
        return;
    }

    pending >>= CAUSEB_IP;
    while (pending) {
        irq = fls(pending) - 1;
        do_IRQ(MIPS_CPU_IRQ_BASE + irq);
        pending &= ~BIT(irq);
    }
}

static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
    struct irq_chip *chip = &ltq_irq_type;
    int i;

    if (hw < MIPS_CPU_IRQ_CASCADE)
        return 0;

    for (i = 0; i < exin_avail; i++)
        if (hw == ltq_eiu_irq[i])
            chip = &ltq_eiu_type;

    irq_set_chip_and_handler(irq, chip, handle_level_irq);

    return 0;
}

static const struct irq_domain_ops irq_domain_ops = {
    .xlate = irq_domain_xlate_onetwocell,
    .map = icu_map,
};

int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
    struct device_node *eiu_node;
#if defined(CONFIG_MIPS_MT_SMP)
    struct device_node *icu1_node;
#endif
    struct resource res;
    int i, ret;

    for (i = 0; i < MAX_IM; i++) {
        if (of_address_to_resource(node, i, &res))
            panic("Failed to get icu0 memory range");

        if (!request_mem_region(res.start, resource_size(&res),
                    res.name))
            pr_err("Failed to request icu0 memory");

// a different name in devicetree
pr_info("%s\n",node->name);

        if (of_node_cmp(node->name, "icu0") == 0) {
            ltq_icu_membase[0][i] = ioremap_nocache(res.start,
                resource_size(&res));
        }
        if (!ltq_icu_membase[0][i])
            panic("Failed to remap icu0 memory");
    }

#if defined(CONFIG_MIPS_MT_SMP)
        //requires a new node, TODO merge with icu0 node?
        icu1_node = of_find_compatible_node(NULL, NULL, "lantiq,icu1");
        for (i = 0; i < MAX_IM; i++) {
                if (of_address_to_resource(icu1_node, i, &res))
                        panic("Failed to get icu1 memory range");

                if (request_mem_region(res.start, resource_size(&res),
                                        res.name) < 0)
                        pr_err("Failed to request icu1 memory");

                if (of_node_cmp(icu1_node->name, "icu1") == 0){
                        ltq_icu_membase[1][i] = ioremap_nocache(res.start,
                                        resource_size(&res));
                }

                if (!ltq_icu_membase[1][i])
                        panic("Failed to remap icu1 memory");

        }
#endif

    /* turn off all irqs by default */
    for (i = 0; i < MAX_IM; i++) {
        /* make sure all irqs are turned off by default */
        ltq_icu_w32(0, i, 0, LTQ_ICU_IM0_IER);
        /* clear all possibly pending interrupts */
        ltq_icu_w32(0, i, ~0, LTQ_ICU_IM0_ISR);
#if defined(CONFIG_MIPS_MT_SMP)
                ltq_icu_w32(1, i, 0, LTQ_ICU_IM0_IER);
                ltq_icu_w32(1, i, ~0, LTQ_ICU_IM0_ISR);
#endif
    }

    mips_cpu_irq_init();

    for (i = 0; i < MAX_IM; i++)
        irq_set_chained_handler(i + 2, ltq_hw_irq_handler);

    if (cpu_has_vint) {
        pr_info("Setting up vectored interrupts\n");
        set_vi_handler(2, ltq_hw0_irqdispatch);
        set_vi_handler(3, ltq_hw1_irqdispatch);
        set_vi_handler(4, ltq_hw2_irqdispatch);
        set_vi_handler(5, ltq_hw3_irqdispatch);
        set_vi_handler(6, ltq_hw4_irqdispatch);
        set_vi_handler(7, ltq_hw5_irqdispatch);
    }

    ltq_domain = irq_domain_add_linear(node,
        (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
        &irq_domain_ops, 0);

#if defined(CONFIG_MIPS_MT_SMP)
    if (cpu_has_vint) {
        pr_info("Setting up IPI vectored interrupts\n");
        set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
        set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
    }
    arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
        &irq_resched);
    arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
#endif

#ifndef CONFIG_MIPS_MT_SMP
    set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
        IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
    set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
        IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif

    /* tell oprofile which irq to use */
    ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);

    /*
     * if the timer irq is not one of the mips irqs we need to
     * create a mapping
     */
    if (MIPS_CPU_TIMER_IRQ != 7)
        irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);

    /* the external interrupts are optional and xway only */
    eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
    if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
        /* find out how many external irq sources we have */
        exin_avail = of_property_count_u32_elems(eiu_node,
                             "lantiq,eiu-irqs");

        if (exin_avail > MAX_EIU)
            exin_avail = MAX_EIU;

        ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
                        ltq_eiu_irq, exin_avail);
        if (ret)
            panic("failed to load external irq resources");

        if (!request_mem_region(res.start, resource_size(&res),
                            res.name))
            pr_err("Failed to request eiu memory");

        ltq_eiu_membase = ioremap_nocache(res.start,
                            resource_size(&res));
        if (!ltq_eiu_membase)
            panic("Failed to remap eiu memory");
    }

    return 0;
}

int get_c0_perfcount_int(void)
{
    return ltq_perfcount_irq;
}
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);

unsigned int get_c0_compare_int(void)
{
    return MIPS_CPU_TIMER_IRQ;
}

static struct of_device_id __initdata of_irq_ids[] = {
    { .compatible = "lantiq,icu", .data = icu_of_init },
    {},
};

void __init arch_init_irq(void)
{
    of_irq_init(of_irq_ids);
}