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Jan 21st, 2020
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VHDL 2.53 KB | None | 0 0
  1. --------------------------------------------------------------------------------
  2.  
  3. --------------------------------------------------------------------------------
  4. LIBRARY ieee;
  5. USE ieee.std_logic_1164.ALL;
  6. use ieee.std_logic_unsigned.all;
  7.  
  8. ENTITY Symulacja IS
  9. END Symulacja;
  10.  
  11. ARCHITECTURE Zmywarka_arch OF Symulacja IS
  12.  
  13.     -- Component Declaration for the Unit Under Test (UUT)
  14.  
  15.     COMPONENT Zmywarka
  16.     PORT(
  17.          reset : IN  std_logic;
  18.          clk : IN  std_logic;
  19.          program : IN  std_logic;
  20.          woda_max : IN  std_logic;
  21.          woda_min : IN  std_logic;
  22.          zawor : OUT  std_logic;
  23.          grzalka : OUT  std_logic;
  24.          pompa : OUT  std_logic;
  25.          nablyszczacz : OUT  std_logic;
  26.             tabletka : OUT std_logic
  27.             );
  28.     END COMPONENT;
  29.    
  30.  
  31.    --Inputs
  32.    signal reset : std_logic := '0';
  33.    signal clk : std_logic := '0';
  34.    signal program : std_logic := '0';
  35.    signal woda_max : std_logic := '0';
  36.    signal woda_min : std_logic := '0';
  37.  
  38.     --Outputs
  39.    signal zawor : std_logic;
  40.    signal grzalka : std_logic;
  41.    signal pompa : std_logic;
  42.    signal nablyszczacz : std_logic;
  43.     signal tabletka : std_logic;
  44.  
  45.    -- Clock period definitions
  46.    constant clk_period : time := 10 ns;
  47.  
  48. BEGIN
  49.  
  50.     -- Instantiate the Unit Under Test (UUT)
  51.    uut: Zmywarka PORT MAP (
  52.           reset => reset,
  53.           clk => clk,
  54.           program => program,
  55.           woda_max => woda_max,
  56.           woda_min => woda_min,
  57.           zawor => zawor,
  58.           grzalka => grzalka,
  59.           pompa => pompa,
  60.           nablyszczacz => nablyszczacz,
  61.              tabletka => tabletka
  62.         );
  63.  
  64.    -- Clock process definitions
  65.    clk_process :process
  66.    begin
  67.         clk <= '0';
  68.         wait for clk_period/2;
  69.         clk <= '1';
  70.         wait for clk_period/2;
  71.    end process;
  72.  
  73.  
  74.    -- Stimulus process
  75.    symulacja: process
  76.    begin
  77.    
  78.         reset <= '0'; wait for clk_period*1.5;
  79.         reset <= '1'; wait for clk_period;
  80.         program <= '1'; wait for clk_period*5;
  81.         woda_max <= '1';
  82.         woda_max <= '0'; wait for clk_period;
  83.         woda_max <= '1'; wait for clk_period;
  84.         woda_max <= '0'; wait for clk_period*7;
  85.         woda_min <= '1'; wait for clk_period;
  86.         woda_min <= '0'; wait for clk_period*10;
  87.         woda_max <= '1'; wait for clk_period;
  88.         woda_max <= '0'; wait for clk_period*10;
  89.         woda_min <= '1';
  90.         woda_min <= '0'; wait for clk_period*10;
  91.         woda_min <= '1'; wait for clk_period*1.7;
  92.         woda_min <= '0'; wait for clk_period*3;
  93.         program <= '0'; wait for clk_period*2;
  94.    
  95.         assert false severity failure;
  96.    end process;
  97.  
  98. END;
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