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- --------------------------------------------------------------------------------
- --------------------------------------------------------------------------------
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- use ieee.std_logic_unsigned.all;
- ENTITY Symulacja IS
- END Symulacja;
- ARCHITECTURE Zmywarka_arch OF Symulacja IS
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT Zmywarka
- PORT(
- reset : IN std_logic;
- clk : IN std_logic;
- program : IN std_logic;
- woda_max : IN std_logic;
- woda_min : IN std_logic;
- zawor : OUT std_logic;
- grzalka : OUT std_logic;
- pompa : OUT std_logic;
- nablyszczacz : OUT std_logic;
- tabletka : OUT std_logic
- );
- END COMPONENT;
- --Inputs
- signal reset : std_logic := '0';
- signal clk : std_logic := '0';
- signal program : std_logic := '0';
- signal woda_max : std_logic := '0';
- signal woda_min : std_logic := '0';
- --Outputs
- signal zawor : std_logic;
- signal grzalka : std_logic;
- signal pompa : std_logic;
- signal nablyszczacz : std_logic;
- signal tabletka : std_logic;
- -- Clock period definitions
- constant clk_period : time := 10 ns;
- BEGIN
- -- Instantiate the Unit Under Test (UUT)
- uut: Zmywarka PORT MAP (
- reset => reset,
- clk => clk,
- program => program,
- woda_max => woda_max,
- woda_min => woda_min,
- zawor => zawor,
- grzalka => grzalka,
- pompa => pompa,
- nablyszczacz => nablyszczacz,
- tabletka => tabletka
- );
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
- -- Stimulus process
- symulacja: process
- begin
- reset <= '0'; wait for clk_period*1.5;
- reset <= '1'; wait for clk_period;
- program <= '1'; wait for clk_period*5;
- woda_max <= '1';
- woda_max <= '0'; wait for clk_period;
- woda_max <= '1'; wait for clk_period;
- woda_max <= '0'; wait for clk_period*7;
- woda_min <= '1'; wait for clk_period;
- woda_min <= '0'; wait for clk_period*10;
- woda_max <= '1'; wait for clk_period;
- woda_max <= '0'; wait for clk_period*10;
- woda_min <= '1';
- woda_min <= '0'; wait for clk_period*10;
- woda_min <= '1'; wait for clk_period*1.7;
- woda_min <= '0'; wait for clk_period*3;
- program <= '0'; wait for clk_period*2;
- assert false severity failure;
- end process;
- END;
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