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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5.  
  6. entity rtl_system is
  7.   generic (
  8.     -- Users to add parameters here
  9.  
  10.     -- User parameters ends
  11.  
  12.     -- Do not modify the parameters beyond this line
  13.     -- Parameters of Axi Slave Bus Interface S_AXI
  14.     C_S_AXI_DATA_WIDTH : integer := 32;
  15.     C_S_AXI_ADDR_WIDTH : integer := 6;
  16.  
  17.     -- Parameters of Axi Master Bus Interface S_AXIS
  18.     C_S_AXIS_TDATA_WIDTH : integer := 32;
  19.  
  20.     -- Parameters of Axi Master Bus Interface M_AXIS
  21.     C_M_AXIS_TDATA_WIDTH : integer := 32;
  22.     C_M_AXIS_START_COUNT : integer := 32
  23.     );
  24.   port (
  25.     -- Users to add ports here
  26.  
  27.     -- User ports ends
  28.  
  29.     -- Do not modify the ports beyond this line
  30.     -- Ports of Axi Slave Bus Interface S_AXI
  31.     s_axi_aclk    : in  std_logic;
  32.     s_axi_aresetn : in  std_logic;
  33.     s_axi_awaddr  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  34.     s_axi_awprot  : in  std_logic_vector(2 downto 0);
  35.     s_axi_awvalid : in  std_logic;
  36.     s_axi_awready : out std_logic;
  37.     s_axi_wdata   : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  38.     s_axi_wstrb   : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
  39.     s_axi_wvalid  : in  std_logic;
  40.     s_axi_wready  : out std_logic;
  41.     s_axi_bresp   : out std_logic_vector(1 downto 0);
  42.     s_axi_bvalid  : out std_logic;
  43.     s_axi_bready  : in  std_logic;
  44.     s_axi_araddr  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  45.     s_axi_arprot  : in  std_logic_vector(2 downto 0);
  46.     s_axi_arvalid : in  std_logic;
  47.     s_axi_arready : out std_logic;
  48.     s_axi_rdata   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  49.     s_axi_rresp   : out std_logic_vector(1 downto 0);
  50.     s_axi_rvalid  : out std_logic;
  51.     s_axi_rready  : in  std_logic;
  52.  
  53.     -- Ports of Axi Streaming Slave Bus Interface S_AXIS
  54.     S_AXIS_ACLK    : in  std_logic;
  55.     S_AXIS_ARESETN : in  std_logic;
  56.     S_AXIS_TREADY  : out std_logic;
  57.     S_AXIS_TDATA   : in  std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
  58.     S_AXIS_TSTRB   : in  std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
  59.     S_AXIS_TLAST   : in  std_logic;
  60.     S_AXIS_TVALID  : in  std_logic;
  61.  
  62.     -- Ports of Axi Streaming Master Bus Interface M_AXIS
  63.     m_axis_aclk    : in  std_logic;
  64.     m_axis_aresetn : in  std_logic;
  65.     m_axis_tvalid  : out std_logic;
  66.     m_axis_tdata   : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
  67.     m_axis_tstrb   : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
  68.     m_axis_tlast   : out std_logic;
  69.     m_axis_tready  : in  std_logic
  70.     );
  71. end rtl_system;
  72.  
  73. architecture arch_imp of rtl_system is
  74.  
  75.   -- component declaration
  76.   component rtl_system_S_AXI is
  77.     generic (
  78.       C_S_AXI_DATA_WIDTH : integer := 32;
  79.       C_S_AXI_ADDR_WIDTH : integer := 6
  80.       );
  81.     port (
  82.       -- User logic configuration registers
  83.       reg0_o        : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  84.       reg1_o        : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  85.       reg2_o        : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  86.       reg3_o        : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  87.       -- Puertos AXI
  88.       S_AXI_ACLK    : in  std_logic;
  89.       S_AXI_ARESETN : in  std_logic;
  90.       S_AXI_AWADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  91.       S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);
  92.       S_AXI_AWVALID : in  std_logic;
  93.       S_AXI_AWREADY : out std_logic;
  94.       S_AXI_WDATA   : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  95.       S_AXI_WSTRB   : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
  96.       S_AXI_WVALID  : in  std_logic;
  97.       S_AXI_WREADY  : out std_logic;
  98.       S_AXI_BRESP   : out std_logic_vector(1 downto 0);
  99.       S_AXI_BVALID  : out std_logic;
  100.       S_AXI_BREADY  : in  std_logic;
  101.       S_AXI_ARADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  102.       S_AXI_ARPROT  : in  std_logic_vector(2 downto 0);
  103.       S_AXI_ARVALID : in  std_logic;
  104.       S_AXI_ARREADY : out std_logic;
  105.       S_AXI_RDATA   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  106.       S_AXI_RRESP   : out std_logic_vector(1 downto 0);
  107.       S_AXI_RVALID  : out std_logic;
  108.       S_AXI_RREADY  : in  std_logic
  109.       );
  110.   end component rtl_system_S_AXI;
  111.  
  112.   component rtl_system_S_AXIS is
  113.   generic (
  114.     -- Users to add parameters here
  115.  
  116.     -- User parameters ends
  117.     -- Do not modify the parameters beyond this line
  118.     -- AXI4Stream sink: Data Width
  119.     C_S_AXIS_TDATA_WIDTH : integer := 32
  120.     );
  121.   port (
  122.     -- Users to add ports here
  123.     dv_o           : out  std_logic;
  124.     data_o         : out  std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
  125.     data_last_o    : out  std_logic;
  126.     clk_i          : in   std_logic;  -- User logic clock.
  127.     rst_o          : out std_logic;   -- Active high.
  128.     -- User ports ends
  129.  
  130.     -- Do not modify the ports beyond this line
  131.     S_AXIS_ACLK    : in  std_logic;
  132.     S_AXIS_ARESETN : in  std_logic;
  133.     S_AXIS_TREADY  : out std_logic;
  134.     S_AXIS_TDATA   : in  std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
  135.     S_AXIS_TSTRB   : in  std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
  136.     S_AXIS_TLAST   : in  std_logic;
  137.     S_AXIS_TVALID  : in  std_logic
  138.     );
  139.     end component rtl_system_S_AXIS;
  140.  
  141.   component rtl_system_M_AXIS is
  142.     generic (
  143.       C_M_AXIS_TDATA_WIDTH : integer := 32
  144.       );
  145.     port (
  146.       -- Users to add ports here
  147.       we_i           : in  std_logic;
  148.       data_i         : in  std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
  149.       data_last_i    : in  std_logic;
  150.       clk_i          : in  std_logic;  -- User logic clock.
  151.       rst_o          : out std_logic;  -- Active high.
  152.       -- Fin puertos de usuario
  153.       M_AXIS_ACLK    : in  std_logic;
  154.       M_AXIS_ARESETN : in  std_logic;
  155.       M_AXIS_TVALID  : out std_logic;
  156.       M_AXIS_TDATA   : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
  157.       M_AXIS_TSTRB   : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
  158.       M_AXIS_TLAST   : out std_logic;
  159.       M_AXIS_TREADY  : in  std_logic
  160.       );
  161.   end component rtl_system_M_AXIS;
  162.  
  163.   signal rst : std_logic;
  164.  
  165.   -- Configuration registers
  166.   signal reg0 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  167.   signal reg1 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  168.   signal reg2 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  169.   signal reg3 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  170.  
  171.   signal data       : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  172.   signal data_last  : std_logic;
  173.   signal dv         : std_logic;
  174.  
  175.   -- For DEBUGGING:
  176.   attribute MARK_DEBUG : string;
  177.   attribute MARK_DEBUG of data      : signal is "TRUE";
  178.   attribute MARK_DEBUG of data_last : signal is "TRUE";
  179.   attribute MARK_DEBUG of dv        : signal is "TRUE";
  180.  
  181. begin
  182.  
  183.  
  184.   -- Instantiation of Axi Bus Interface S_AXI
  185.   rtl_system_S_AXI_inst: rtl_system_S_AXI
  186.     generic map (
  187.       C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
  188.       C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
  189.       )
  190.     port map (
  191.       reg0_o        => reg0,
  192.       reg1_o        => reg1,
  193.       reg2_o        => reg2,
  194.       reg3_o        => reg3,
  195.       S_AXI_ACLK    => s_axi_aclk,
  196.       S_AXI_ARESETN => s_axi_aresetn,
  197.       S_AXI_AWADDR  => s_axi_awaddr,
  198.       S_AXI_AWPROT  => s_axi_awprot,
  199.       S_AXI_AWVALID => s_axi_awvalid,
  200.       S_AXI_AWREADY => s_axi_awready,
  201.       S_AXI_WDATA   => s_axi_wdata,
  202.       S_AXI_WSTRB   => s_axi_wstrb,
  203.       S_AXI_WVALID  => s_axi_wvalid,
  204.       S_AXI_WREADY  => s_axi_wready,
  205.       S_AXI_BRESP   => s_axi_bresp,
  206.       S_AXI_BVALID  => s_axi_bvalid,
  207.       S_AXI_BREADY  => s_axi_bready,
  208.       S_AXI_ARADDR  => s_axi_araddr,
  209.       S_AXI_ARPROT  => s_axi_arprot,
  210.       S_AXI_ARVALID => s_axi_arvalid,
  211.       S_AXI_ARREADY => s_axi_arready,
  212.       S_AXI_RDATA   => s_axi_rdata,
  213.       S_AXI_RRESP   => s_axi_rresp,
  214.       S_AXI_RVALID  => s_axi_rvalid,
  215.       S_AXI_RREADY  => s_axi_rready
  216.       );
  217.  
  218.   -- Instantiation of Axi Bus Interface M_AXIS
  219.   rtl_system_M_AXIS_inst: rtl_system_M_AXIS
  220.     generic map (
  221.       C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH
  222.       )
  223.     port map (
  224.       -- Users to add ports here
  225.       we_i           => dv,
  226.       data_i         => data,
  227.       data_last_i    => data_last,
  228.       clk_i          => m_axis_aclk,  -- Replace with user logic clock
  229.       rst_o          => open,         -- Active high.
  230.       -- Fin puertos de usuario
  231.       M_AXIS_ACLK    => m_axis_aclk,
  232.       M_AXIS_ARESETN => m_axis_aresetn,
  233.       M_AXIS_TVALID  => m_axis_tvalid,
  234.       M_AXIS_TDATA   => m_axis_tdata,
  235.       M_AXIS_TSTRB   => m_axis_tstrb,
  236.       M_AXIS_TLAST   => m_axis_tlast,
  237.       M_AXIS_TREADY  => m_axis_tready
  238.       );
  239.  
  240.   -- Instantiation of Axi Bus Interface S_AXIS
  241.   rtl_system_S_AXIS_inst: rtl_system_S_AXIS
  242.     generic map (
  243.       C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
  244.       )
  245.     port map (
  246.       -- Users to add ports here
  247.       dv_o           => dv,
  248.       data_o         => data,
  249.       data_last_o    => data_last,
  250.       clk_i          => m_axis_aclk,  -- Replace with user logic clock
  251.       rst_o          => open,         -- Active high.
  252.       -- Fin puertos de usuario
  253.       S_AXIS_ACLK    => s_axis_aclk,
  254.       S_AXIS_ARESETN => s_axis_aresetn,
  255.       S_AXIS_TVALID  => s_axis_tvalid,
  256.       S_AXIS_TDATA   => s_axis_tdata,
  257.       S_AXIS_TSTRB   => s_axis_tstrb,
  258.       S_AXIS_TLAST   => s_axis_tlast,
  259.       S_AXIS_TREADY  => s_axis_tready
  260.       );
  261.      
  262.   -- User logic start here
  263.  
  264.  
  265. end arch_imp;
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