rot_svjetlo

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-- Company:
-- Engineer:
--
-- Create Date:    11:42:36 12/15/2020
-- Design Name:
-- Module Name:    rot2_svjetlo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
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-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
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--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rot2_svjetlo is

port(clk: in STD_LOGIC; --definiran ulaz
      ledica: out STD_LOGIC_VECTOR(7 downto 0)); -- definiran izlaz za ledice sa MSB s desne strane (tj. prva ledica na sklopu je s desne strane

end rot2_svjetlo;

architecture Behavioral of rot2_svjetlo is

type stanje is(S0,S1,S2,S3,S4,S5,S6,S7); --definirana 7 stanja zbog 7 ledica
signal trenutno, buduce:stanje; -- definirani signali
signal clk_0:STD_LOGIC;

begin
A1: entity work.freqDivGen port map(clk,clk_0); --pozivanje frenq_div_gen-a s izlaznim signalom clk_0
process(clk_0)
begin
if(clk_0 'event and clk_0='1')then -- proces koji govori kada ce preci iz trenutnog stanja u buduce
trenutno<=buduce;
end if;
end process;

process(trenutno)--definirani izlazi za stanja
begin
case trenutno is
when S0=>
ledica<="00000011";
buduce<=S1;

when S1=>
ledica<="00000110";
buduce<=S2;

when S2=>
ledica<="00001100";
buduce<=S3;

when S3=>
ledica<="00011000";
buduce<=S4;

when S4=>
ledica<="00110000";
buduce<=S5;

when S5=>
ledica<="01100000";
buduce<=S6;

when S6=>
ledica<="11000000";
buduce<=S7;

when S7=>
ledica<="10000001";
buduce<=S0;

end case;
end process;
end Behavioral;