---------------- bin2hex ----------------
library ieee;
use ieee.std_logic_1164.all;

entity bin2hex is
port(
    bin : in std_logic_vector(3 downto 0);
    seg : out std_logic_vector(6 downto 0));
end bin2hex;

architecture structural of bin2hex is
begin
    case_bin: process (bin) -- case statements oprettes
    begin
        case(bin) is -- cases erklæres
        when "0000" => seg <= "1000000"; -- hexdisplay viser 0
        when "0001" => seg <= "1111001"; -- hexdisplay viser 1
        when "0010" => seg <= "0100100"; -- hexdisplay viser 2
        when "0011" => seg <= "0110000"; -- hexdisplay viser 3
        when "0100" => seg <= "0011001"; -- hexdisplay viser 4
        when "0101" => seg <= "0010010"; -- hexdisplay viser 5
        when "0110" => seg <= "0000010"; -- hexdisplay viser 6
        when "0111" => seg <= "1111000"; -- hexdisplay viser 7
        when "1000" => seg <= "0000000"; -- hexdisplay viser 8
        when "1001" => seg <= "0010000"; -- hexdisplay viser 9
        when "1010" => seg <= "0001000"; -- hexdisplay viser A
        when "1011" => seg <= "0000011"; -- hexdisplay viser b
        when "1100" => seg <= "1000110"; -- hexdisplay viser C
        when "1101" => seg <= "0100001"; -- hexdisplay viser d
        when "1110" => seg <= "0000110"; -- hexdisplay viser E
        when "1111" => seg <= "0001110"; -- hexdisplay viser F
        end case; -- case conditions er nu erklæret
    end process case_bin; -- process afsluttes
end structural;




---------- bin2hex_tester -----------
library ieee;
use ieee.std_logic_1164.all;

entity bin2hex_tester is
port(
    SW      : in std_logic_vector(3 downto 0);
    HEX0    : out std_logic_vector(6 downto 0));
end bin2hex_tester;

architecture structural of bin2hex_tester is
begin
I1: entity work.bin2hex
    port map(
    bin => SW(3 downto 0), -- bin forbindes til switches 3 - 0
    seg => HEX0(6 downto 0)); -- Sseg forbindes til hexdisplay0
end structural;