SPI_BUS

// SPORTバス フラッシュメモリに切り替え
static void change_spi_bus(void)
{
    // SPORTバスをフラッシュメモリに切り替え
    *pPORTF_FER   |= PF4;
    *pPORTFIO_DIR &= ~PF4;
    *pPORTFIO_CLEAR  = PF4;

    *pPORTGIO_DIR &= ~PG12;
    *pPORTGIO_CLEAR = PG12;

    *pPORTF_FER   &= ~PF8;
    *pPORTFIO_SET  = PF8;
    *pPORTFIO_DIR |= PF8;

    // SPI SCK, MOSI, MISO
    *pPORTF_FER   |= PF13 | PF14 | PF15;
    *pPORTF_MUX   &= ~(PF13 | PF14 | PF15);

    // SPI初期化
    *pSPI0_BAUD    = 2;
    *pSPI0_CTL     = SPE | MSTR | EMISO | TDBR_CORE;
    *pSPI0_FLG     = 0;
    ssync();
}

// SPORTバス 元に戻す
static void return_spi_bus(void)
{
    // SPORTバスをADAU1361に切り替え
    *pPORTF_FER   |= PF8;
    *pPORTFIO_CLEAR = PF8;
    *pPORTFIO_DIR &= ~PF8;

    *pPORTF_FER   &= ~PF4;
    *pPORTFIO_DIR |= PF4;
    *pPORTFIO_SET  = PF4;

    *pPORTGIO_DIR |= PG12;
    *pPORTGIO_SET = PG12;

    *pSPI0_CTL   = 0;
    // SPI SCK, MOSI, MISO
    *pPORTF_FER   |= PF13 | PF14 | PF15;
    *pPORTF_MUX   &= ~(PF13 | PF14 | PF15);

    // SPI初期化
    *pSPI0_BAUD = 5;
    *pSPI0_FLG   = 0;
    *pSPI0_CTL   = SPE | MSTR | EMISO | TDBR_CORE;
    ssync();
}