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usi2g.asm Serial tx seems to work via USI

prjbrook
Oct 12th, 2014
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  1. Seems to work, the tx of serial byte using usi. Needs reversing and splitting of serial byte first.
  2. .include "tn85def.inc" ;usi2g: reverse bits seem ok. Now splitting into two bytes
  3. again:
  4. ldi r16, low(RAMEND)
  5. out SPL, r16
  6. ldi r16,high(RAMEND)
  7. out SPH, r16
  8. ;rjmp split62
  9. ;ldi r17,17
  10. ;ldi r18,18
  11. ;ldi r16,$a6
  12. ;rcall split62
  13. ;nop
  14. ;rcall reverseBits
  15. ;ag1:
  16. ;rjmp ag1
  17. ldi r16,$ff
  18. out DDRB,r16
  19. out PORTB,r16
  20. ldi r19,(1<<USIWM0)|(0<<USICS0) ;need this otherwise msb not initially joined to D0
  21. out USICR,r19
  22. ldi r16,$a6 ;!!<--- this works. Comes out as $a6, after reversing and splitiing, on terminal at about 1Hz
  23. rcall reverseBits
  24. rcall split62
  25. rcall SPITransfer_Fast2
  26. mov r16,r17
  27. rcall SPITransfer_Fast2
  28. rjmp here
  29.  
  30.  
  31.  
  32. ldi r16,$a5
  33. rcall SPITransfer_Fast2
  34. ldi r16,$bf
  35. rcall SPITransfer_Fast2
  36.  
  37. ;rcall SPITransfer
  38. here:
  39. rcall oneSec
  40. rcall oneSec
  41. rcall oneSec
  42. rjmp again
  43.  
  44.  
  45.  
  46. ;-----------------------------------
  47. SPITransfer_Fast2:
  48. out USIDR,r16
  49. ;fin2:
  50. ;rjmp fin2
  51. ;ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
  52. ldi r19,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
  53. ldi r18,8
  54. upt2:
  55. ;out USICR,r16 ; MSB
  56. rcall oneBitTime
  57. ;rcall oneSec
  58. ;rjmp upt2
  59. out USICR,r19
  60. up3:
  61. ;rjmp up3
  62. dec r18
  63. brne upt2
  64.  
  65. ret
  66. ;---------------------------------------
  67.  
  68. halfBitTime: ;better name for this delay. Half of 1/600
  69. ;myDelay1200:
  70. ;ldi r21,13 ; 13 works for m328 at 16Mhz
  71. push r20
  72. push r21
  73. ldi r21,7 ;try 7 for tiny85 at 8Hmz
  74. ldi r20,130 ;r20,21 at 130,7 give 833uS. Good for 600baud at 8Mhz
  75. starthbt:
  76. inc r20
  77. nop
  78. brne starthbt
  79. dec r21
  80. brne starthbt
  81. pop r21
  82. pop r20
  83. ret
  84. ;--------------------------------------------------
  85. oneBitTime:
  86. rcall halfBitTime
  87. rcall halfBitTime
  88. ret
  89. ;---------------------------------
  90. delay100ms: ;handy; delay for about 0.1 sec = 100 ms
  91. ;header endif_1,10,"delay100ms"
  92. ;delay100ms:
  93. ;.ifdef testing
  94. ; ldi r16,1
  95. ;.else
  96. push r16
  97. ldi r16,60
  98. .;endif
  99. upd100:
  100. rcall oneBitTime
  101. dec r16
  102. brne upd100
  103. pop r16
  104. ret ;after about a tenth of a second
  105. ;------------------------
  106. oneSec:
  107. ;jmp finsec ;take out when not simulating
  108. push r17
  109. ldi r17,5
  110. upones:
  111. rcall delay100ms
  112. dec r17
  113. brne upones
  114. pop r17
  115. finsec:
  116. ret
  117. ;-----------------------------------
  118. reverseBits: ;r16 gets reversed
  119. push r17
  120. push r18
  121. ldi r18,8
  122. ;ldi r16,$a6
  123. ldi r17,0
  124. uprb:
  125.  
  126. lsl r16
  127. ror r17
  128. dec r18
  129. brne uprb
  130. uprb2:
  131. mov r16,r17
  132. pop r18
  133. pop r17
  134. ret
  135. ;-----------------------
  136. split62: ;split r16 into two bytes, r16 and r17 where r16 contains first 6 bits preceded by
  137. ; by 10, the last stop bit then start bit. Last two bits go into r17 followed by 6 1's. ie 6 stop bits.
  138. ;ldi r16,$f0. Wrecks r16,17
  139. ldi r17,$ff
  140. clc
  141. ror r16
  142. ror r17
  143. sec
  144. ror r16
  145. ror r17
  146. ret
  147. rjmp split62
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