dff1_in : component d_flop port map(set => '1', reset => '1', d => p_in(0), clk => rck, q => dff1_q(0), not_q => dff1_not_q(0));
  dff2_in : component d_flop port map(set => '1', reset => '1', d => p_in(1), clk => rck, q => dff1_q(1), not_q => dff1_not_q(1));
  dff3_in : component d_flop port map(set => '1', reset => '1', d => p_in(2), clk => rck, q => dff1_q(2), not_q => dff1_not_q(2));
  dff4_in : component d_flop port map(set => '1', reset => '1', d => p_in(3), clk => rck, q => dff1_q(3), not_q => dff1_not_q(3));
  dff5_in : component d_flop port map(set => '1', reset => '1', d => p_in(4), clk => rck, q => dff1_q(4), not_q => dff1_not_q(4));
  dff6_in : component d_flop port map(set => '1', reset => '1', d => p_in(5), clk => rck, q => dff1_q(5), not_q => dff1_not_q(5));
  dff7_in : component d_flop port map(set => '1', reset => '1', d => p_in(6), clk => rck, q => dff1_q(6), not_q => dff1_not_q(6));
  dff8_in : component d_flop port map(set => '1', reset => '1', d => p_in(7), clk => rck, q => dff1_q(7), not_q => dff1_not_q(7));

  set(0)   <= not (dff1_q(0) and not srload);
  reset(0) <= not (not srclr or (not srload and dff1_not_q(0)));
  set(1)   <= not (dff1_q(1) and not srload);
  reset(1) <= not (not srclr or (not srload and dff1_not_q(1)));
  set(2)   <= not (dff1_q(2) and not srload);
  reset(2) <= not (not srclr or (not srload and dff1_not_q(2)));
  set(3)   <= not (dff1_q(3) and not srload);
  reset(3) <= not (not srclr or (not srload and dff1_not_q(3)));
  set(4)   <= not (dff1_q(4) and not srload);
  reset(4) <= not (not srclr or (not srload and dff1_not_q(4)));
  set(5)   <= not (dff1_q(5) and not srload);
  reset(5) <= not (not srclr or (not srload and dff1_not_q(5)));
  set(6)   <= not (dff1_q(6) and not srload);
  reset(6) <= not (not srclr or (not srload and dff1_not_q(6)));
  set(7)   <= not (dff1_q(7) and not srload);
  reset(7) <= not (not srclr or (not srload and dff1_not_q(7)));

  dff1_out : component d_flop port map(set => set(0), reset => reset(0), d => ser, clk => srck, q => q_output(0), not_q => not_q_output(0));

  dff2_out : component d_flop port map(set => set(1), reset => reset(1), d => q_output(0), clk => srck, q => q_output(1), not_q => not_q_output(1));
  dff3_out : component d_flop port map(set => set(2), reset => reset(2), d => q_output(1), clk => srck, q => q_output(2), not_q => not_q_output(2));
  dff4_out : component d_flop port map(set => set(3), reset => reset(3), d => q_output(2), clk => srck, q => q_output(3), not_q => not_q_output(3));
  dff5_out : component d_flop port map(set => set(4), reset => reset(4), d => q_output(3), clk => srck, q => q_output(4), not_q => not_q_output(4));
  dff6_out : component d_flop port map(set => set(5), reset => reset(5), d => q_output(4), clk => srck, q => q_output(5), not_q => not_q_output(5));
  dff7_out : component d_flop port map(set => set(6), reset => reset(6), d => q_output(5), clk => srck, q => q_output(6), not_q => not_q_output(6));
  dff8_out : component d_flop port map(set => set(7), reset => reset(7), d => q_output(6), clk => srck, q => q_output(7), not_q => not_q_output(7));

  Q <= q_output;