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ROM from MUX code

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Jun 5th, 2018
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VHDL 0.74 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4.  
  5. entity rom_2 is
  6. generic(
  7.     address_length: natural := 2;
  8.     data_length: natural := 4
  9. );
  10. port(
  11.     clock: in std_logic;
  12.     rom_enable: in std_logic;
  13.     address: in std_logic_vector((address_length - 1) downto 0);
  14.     data_output: out std_logic_vector ((data_length - 1) downto 0)
  15. );
  16. end rom_2;
  17.  
  18. architecture arch of rom_2 is
  19.  
  20. begin
  21.  
  22. process(clock) is
  23. begin
  24.     if(rising_edge(clock) and rom_enable = '1') then
  25.         if(address="00") then
  26.             data_output <= "1001";
  27.         elsif(address="01") then
  28.                 data_output <= "0110";
  29.         elsif(address="10") then
  30.                 data_output <= "0000";
  31.         elsif(address="11") then
  32.                 data_output <= "1111";
  33.         end if;
  34.     end if;
  35. end process;
  36.  
  37. end arch;
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