a95x f3 air

TE: 1990321

BL2 Built : 20:29:41, Jun 18 2019. g12a ga659aac - luan.yuan@droid15-sz

Board ID = 1
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
OTP_ARB=00000001
DDR driver_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019 20:29:37
board id: 1
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
FIP HDR CHK: 0xffffffff ADDR 0xfffd0000
reset...
SM1:BL:511f6b:81ca2f;FEAT:B2F839B2:202B2060;POC:F;RCY:0;