library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bspline_pckg.all;

-- p = (a +/- b) * c    + if addsub = '1', - if addsub = '0'
-- a and b must be same width

entity preadd_mult_round is

    generic(
            Wa : natural;
            Wb : natural;
            Wc : natural;
            Wo : natural;
            round_mode : string
            );
    port(
        clk : in std_logic;
        rst : in std_logic;
        addsub : in std_logic;
        a : in signed(Wa-1 downto 0);
        b : in signed(Wb-1 downto 0);
        c : in signed(Wc-1 downto 0);
        p : out signed(Wo-1 downto 0)
        );

end entity;

architecture rtl of preadd_mult_round is

    constant zeros : signed(Wo-1 downto 1) := (others => '0');
    constant Ws : natural := max(Wa, Wb);

    signal c_del : signed(Wc-1 downto 0);
    signal sum  : signed(Ws-1 downto 0);
    signal mult : signed(Ws+Wc-1 downto 0);
    signal mult_r : signed(Wo-1 downto 0);

begin

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                sum <= (others => '0');
            else
                if addsub = '1' then
                    sum <= resize(a, Ws) + resize(b, Ws);
                else
                    sum <= resize(a, Ws) - resize(b, Ws);
                end if;
            end if;
        end if;
    end process;

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                c_del <= (others => '0');
            else
                c_del <= c;
            end if;
        end if;
    end process;

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                mult <= (others => '0');
            else
                mult <= c_del * sum;
            end if;
        end if;
    end process;

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                mult_r <= (others => '0');
            else
                if round_mode = "trunc" then
                    mult_r <= mult(Ws+Wc-2 downto Ws+Wc-Wo-1);
                else
                    mult_r <= mult(Ws+Wc-2 downto Ws+Wc-Wo-1) + (zeros & mult(Ws+Wc-Wo-2));
                end if;
            end if;
        end if;
    end process;

    p <= mult_r;

end rtl;