Assignment-VHDL-Passed-Pin

# PlanAhead Generated IO constraints

NET "A[3]" LOC = P15;
NET "A[2]" LOC = P17;
NET "A[1]" LOC = P18;
NET "A[0]" LOC = P20;
NET "B[3]" LOC = P21;
NET "B[2]" LOC = P23;
NET "B[1]" LOC = P24;
NET "B[0]" LOC = P25;
NET "SignA" LOC = P8;
NET "SignB" LOC = P11;
NET "Operator" LOC = P10;
NET "clk" LOC = P127;

NET "OutLEDSign[2]" LOC = P36;
NET "OutLEDSign[1]" LOC = P40;
NET "OutLEDSign[0]" LOC = P41;


NET "COM[0]" LOC = P5;
NET "COM[1]" LOC = P6;
NET "COM[2]" LOC = P131;

NET "seg[0]" LOC = P4;
NET "seg[1]" LOC = P2;
NET "seg[2]" LOC = P1;
NET "seg[3]" LOC = P141;
NET "seg[4]" LOC = P140;
NET "seg[5]" LOC = P137;
NET "seg[6]" LOC = P135;

NET "OutLEDA[3]" LOC = P26;
NET "OutLEDA[2]" LOC = P27;
NET "OutLEDA[1]" LOC = P28;
NET "OutLEDA[0]" LOC = P30;

NET "OutLEDB[3]" LOC = P31;
NET "OutLEDB[2]" LOC = P32;
NET "OutLEDB[1]" LOC = P33;
NET "OutLEDB[0]" LOC = P35;


NET "CSum[4]" LOC = P44;
NET "CSum[3]" LOC = P46;
NET "CSum[2]" LOC = P47;
NET "CSum[1]" LOC = P50;
NET "CSum[0]" LOC = P51;