emi

module d_ff(
  input clk,rst,d,
  output reg q);
always @ (posedge clk, posedge rst)
if(rst==1) q<=0;
else
  q<=d;
endmodule

module d_ffinv(
  input clk,rst,d,
  output reg q);
always @ (posedge clk, posedge rst)
if(rst==1) q<=1;
else
  q<=d;
endmodule

module fdivby3(
  input c_up,clr,clk,rst,
  output fdclk
  );
  localparam S0 = 2'd0;
  localparam S1 = 2'd1;
  localparam S2 = 2'd2;

  wire [2:0] st;
  wire [2:0] st_nxt;

  assign st_nxt[S0] = (st[S0] & ((~c_up) | clr)) | (st[S1] & clr) | (st[S2] & (c_up | clr));
  assign st_nxt[S1] = (st[S0] & c_up & (~clr)) | (st[S1] & (~c_up) & (~clr));
  assign st_nxt[S2] = (st[S1] & c_up & (~clr)) | (st[S2] & (~c_up) & (~clr));

  d_ffinv inst0 (.clk(clk),.rst(rst),.d(st_nxt[S0]),.q(st[S0]));
  d_ff inst1 (.clk(clk),.rst(rst),.d(st_nxt[S1]),.q(st[S1]));
  d_ff inst2 (.clk(clk),.rst(rst),.d(st_nxt[S2]),.q(st[S2]));
  assign fdclk =st[S0];

endmodule

module fdivby3_tb;
  reg clk,rst,clr,c_up;
  wire fdclk;

  fdivby3 inst(.clk(clk),.rst(rst),.clr(clr),.c_up(c_up),.fdclk(fdclk));

  localparam CLK_PERIOD=100, RUNNING_CYCLES=17, RST_DURATION=25;
  initial begin
    $display("time\tclk\trst_b\tclr\tc_up\tfdclk");
    $monitor("%5t\t%b\t%b\t%b\t%b\t%b",$time,clk,rst,clr,c_up,fdclk);
    clk=0;
    repeat (2*RUNNING_CYCLES) #(CLK_PERIOD/2) clk=~clk;
  end

  initial begin
    rst=1;
    #RST_DURATION rst=0;
  end

  initial begin
    clr = 0;
    #(4*CLK_PERIOD) clr=~clr;
    #(CLK_PERIOD) clr=~clr;
  end

  initial begin
    c_up = 1;
    #(6*CLK_PERIOD) c_up=~c_up;
    #(CLK_PERIOD) c_up=~c_up;
    #(4*CLK_PERIOD) c_up=~c_up;
    #(2*CLK_PERIOD) c_up=~c_up;
  end
endmodule