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VeriLog
0.17 KB
| None
|
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always
@
(
posedge
clk
or
negedge
reset
)
begin
if
(
clk
&&
!
reset
)
begin
stage
<=
stage
+
1
;
en
<=
1
;
elseif
(
reset
)
begin
stage
<=
0
;
en
<=
0
;
end
end
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