when read =>
  if( req = "001") then
    next_state <= read;
    licz <= '0';
  elsif (req = "010") then
    next_state <= compare;
    licz <= '1';
  elsif (req = "100") then
    next_state <= write1;
    licz <= '0';
  else
    next_state <= idle;
    licz <= '0';
  end if;
  enable <= "00";
  drive <= '1';
  creset <= '0';


when write1 =>
  next_state <= write2;
  enable <= "01";
  licz <= '0';
  drive <= '0';
  creset <= '1';


when write2 =>

  if (req = "100") then
    next_state <= write1;
    enable <="10";
    licz <= '0';


  elsif (req = "001") then
    next_state <= read;
    enable <= "00";
    licz <= '0';

  elsif (req = "010") then
    next_state <= compare;
    enable <= "00";
    licz <= '1';


  else
    next_state <= idle;
    enable <= "00";
    licz <= '0';

  end if;

	 drive <= '0';
	 creset <= '0';

when compare =>
  if (req = "010") then
    next_state <= compare;
    licz <= '1';
  elsif (req = "100") then
    next_state <= write1;
    licz <= '0';

  elsif (req = "001") then
    next_state <= read;
    licz <= '0';

  else
    next_state <= idle;
    licz <= '0';

   end if;
    enable <= "00";
    drive <= '0';
    creset <= '0';