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- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- USE ieee.numeric_std.ALL;
- ENTITY LogicalStep_Lab4_top IS PORT
- (
- clkin_50 : in std_logic;
- rst_n : in std_logic;
- pb : in std_logic_vector(3 downto 0);
- sw : in std_logic_vector(7 downto 0); -- The switch inputs
- leds : out std_logic_vector(7 downto 0); -- for displaying the switch content
- seg7_data : out std_logic_vector(6 downto 0); -- 7-bit outputs to a 7-segment
- seg7_char1 : out std_logic; -- seg7 digi selectors
- seg7_char2 : out std_logic -- seg7 digi selectors
- );
- END LogicalStep_Lab4_top;
- ARCHITECTURE SimpleCircuit OF LogicalStep_Lab4_top IS
- ----------------------------------------------------------------------------------------------------
- CONSTANT SIM : boolean := FALSE; -- set to TRUE for simulation runs otherwise keep at 0.
- CONSTANT CLK_DIV_SIZE : INTEGER := 26; -- size of vectors for the counters
- SIGNAL Main_CLK : STD_LOGIC; -- main clock to drive sequencing of State Machine
- SIGNAL bin_counter : UNSIGNED(CLK_DIV_SIZE-1 downto 0); -- := to_unsigned(0,CLK_DIV_SIZE); -- reset binary counter to zero
- ----------------------------------------------------------------------------------------------------
- component U_D_Bin_Counter8bit port(
- CLK : in std_logic := '0';
- RESET_n : in std_logic := '0';
- CLK_EN : in std_logic := '0';
- UP1_DOWN0 : in std_logic := '0';
- COUNTER_BITS : out std_logic_vector(7 downto 0)
- );
- end component;
- component Bidir_shift_reg port(
- CLK : in std_logic := '0';
- RESET_n : in std_logic := '0';
- CLK_EN : in std_logic := '0';
- LEFT0_RIGHT1 : in std_logic := '0';
- REG_BITS : out std_logic_vector(3 downto 0)
- );
- end component;
- component MOORE_SM1 port(
- CLK : in std_logic := '0';
- RESET_n : in std_logic := '0';
- EXT_BUTTON : in std_logic := '0';
- EXT_ENBL : in std_logic := '0';
- CLK_EN : out std_logic;
- LEFT_RIGHT : out std_logic;
- GRAP_ENBL : out std_logic;
- EXTENDER_OUT : out std_logic
- );
- end component;
- component MOORE_SM2 port(
- CLK : in std_logic := '0';
- RESET_n : in std_logic := '0';
- GRAP_BUTTON : in std_logic := '0';
- GRAP_ENBL : in std_logic := '0';
- GRAP_ON : out std_logic
- );
- end component;
- component Mealy_SM port(
- clk_input, rst_n, x_motion, x_LT, x_ET, x_GT, ext_out : IN std_logic;
- clk_en, UD_en, ext_en, error : OUT std_logic
- );
- end component;
- component mux port(
- AL_1: in std_logic_vector (3 downto 0);
- CURRENT_X : in std_logic_vector (3 downto 0);
- TARGET_X : in std_logic_vector (3 downto 0);
- PB : in std_logic;
- OUT1 : out std_logic_vector (3 downto 0)
- );
- end component;
- signal x_TARGET : std_logic_vector(7 downto 4);
- signal Y_TARGET : std_logic_vector(3 downto 0);
- signal EXT_BUT : std_logic; --EXTENDER TOGGLE
- signal GRAP_BUT : std_logic; --GRAPPLER TOGGLE
- signal EXT_ENBL : std_logic;
- signal GRAP_ENBL : std_logic;
- signal EXT_LED : std_logic_vector(7 downto 4); -- e
- signal GRAP_LED : std_logic;
- signal grappler_on : std_logic;
- -- signal own_use : std_logic_vector(2 downto 1);
- signal DIGIT1 : std_logic;
- signal DIGIT2 : std_logic;
- -- for Moore_SM
- signal LR : std_logic;
- signal EXT_OUT : std_logic;
- signal GRAP_ON : std_logic;
- signal CLK_EN : std_logic;
- BEGIN
- -- input signals
- X_TARGET <= sw(7 downto 4);
- Y_TARGET <= sw(3 downto 0);
- x_drive_en <= pb(3);
- y_drive_en <= pb(2);
- EXT_BUT <= pb(1); -- CLK_EN
- GRAP_BUT <= pb(0); -- Left0_Right1 / Up1_Down0
- EXT_ENBL <= '1';
- EXT_OUT <= '0';
- --output signals
- seg7_char1 <= DIGIT1;
- seg7_char2 <= DIGIT2;
- leds(7 downto 4) <= EXT_LED;
- leds(3) <= GRAP_LED;
- MOORE_EXTEND: Moore_SM1 port map(Main_CLK, rst_n, EXT_BUT, EXT_ENBL, CLK_EN, LR, GRAP_ENBL, EXT_OUT);
- MOORE_RETRACT: Moore_SM2 port map(Main_CLK, rst_n, GRAP_BUT, GRAP_ENBL, GRAP_LED);
- BIT_SHIFT: Bidir_shift_reg port map(Main_CLK, rst_n, CLK_EN, LR, EXT_LED);
- --SEVEN_SEGMENT_1: SevenSegment port map(hex_A, seg7_A); -- X_TARGET
- --SEVEN_SEGMENT_2: SevenSegment port map(hex_B, seg7_B); -- Y_TARGET
- --SEVEN_SEGMENT_MUX: segment7_mux port map(clkin_50, seg7_A, seg7_B, seg7_data, seg7_char2, seg7_char1);
- --INST1: Bidir_shift_reg port map(clkin_50, rst_n, ext_toggle, grap_toggle, temp); -- TBD needs to be replaced -- clkin_50 replace w Main_CLK ???
- --INST1: U_D_Bin_Counter8bit port map(clkin_50, rst_n, ext_toggle, grap_toggle, temp); ---------------------------
- --MEALY1: Mealy_SM port map(Main_CLK, rst_n, ); -- x MOTION
- --MEALY2: Mealy_SM port map(Main_CLK, rst_n, ); -- Y MOTION
- -- CLOCKING GENERATOR WHICH DIVIDES THE INPUT CLOCK DOWN TO A LOWER FREQUENCY
- BinCLK: PROCESS(clkin_50, rst_n) is
- BEGIN
- IF (rising_edge(clkin_50)) THEN -- binary counter increments on rising clock edge
- bin_counter <= bin_counter + 1;
- END IF;
- END PROCESS;
- Clock_Source:
- Main_Clk <=
- clkin_50 when sim = TRUE else -- for simulations only
- std_logic(bin_counter(23)); -- for real FPGA operation
- ---------------------------------------------------------------------------------------------------
- END SimpleCircuit;
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