test_corrected.v

module test(clk, rst_n);
    input clk, rst_n;
    reg STAR;
    localparam S0=0, S1=1;

    always @(posedge clk or negedge rst_n)
        if (rst_n==0)
            STAR <= S0;
        else
            casex(STAR)
                S0: STAR <= S1;
                S1: STAR <= S0;
            endcase
endmodule