library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY zbrajalo IS PORT(
	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	oper: IN STD_LOGIC;
	r: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	cout: OUT STD_LOGIC
);
END zbrajalo;

ARCHITECTURE arch OF zbrajalo IS
component primitiv PORT(
	a: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	b: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	r: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	cin: IN STD_LOGIC;
	cout: OUT STD_LOGIC;
	oper: IN STD_LOGIC
);
end component;
signal i: std_logic_vector(2 downto 0);
BEGIN
f0: primitiv PORT MAP(a(1 downto 0),b(1 downto 0),r(1 downto 0),oper,i(0),oper);
f1: primitiv PORT MAP(a(3 downto 2),b(3 downto 2),r(3 downto 2),i(0),i(1),oper);
f2: primitiv PORT MAP(a(5 downto 4),b(5 downto 4),r(5 downto 4),i(1),i(2),oper);
f3: primitiv PORT MAP(a(7 downto 6),b(7 downto 6),r(7 downto 6),i(2),cout,oper);

END arch;