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-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "12/11/2019 09:24:30"

-- Vhdl Test Bench template for design  :  oppg1_SynkOgPuls
--
-- Simulation tool : ModelSim-Altera (VHDL)
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY oppg1_SynkOgPuls_vhd_tst IS
END oppg1_SynkOgPuls_vhd_tst;
ARCHITECTURE oppg1_SynkOgPuls_arch OF oppg1_SynkOgPuls_vhd_tst IS
-- constants
-- signals
SIGNAL adresse : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL brytere : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL clock_50 : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL status : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL status_pf : STD_LOGIC_VECTOR(2 DOWNTO 0);

signal key0 : std_logic;
COMPONENT oppg1_SynkOgPuls
	PORT (
	adresse : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	brytere : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	clock_50 : IN STD_LOGIC;
	reset : IN STD_LOGIC;
	status : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	status_pf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	i1 : oppg1_SynkOgPuls
	PORT MAP (
-- list connections between master ports and signals
	adresse => adresse,
	brytere => brytere,
	clock_50 => clock_50,
	reset => reset,
	status => status,
	status_pf => status_pf
	);

status(0) <= key0;
status(1) <= '1';
status(2) <= '1';

klokke : process
begin
	clock_50 <= '0';
	loop
		wait for 10 ns;
		clock_50 <= not clock_50;
	end loop;
wait;
end process klokke;

rst : process
begin

reset <= '0';
for i in 1 to 2 loop
wait until clock_50 ='1';
end loop;
reset <= '1';

wait;
end process rst;


status_og_brytere : PROCESS
-- variable declarations
BEGIN
        brytere(7 downto 0) <= "11000011";
	wait for 300 ns; brytere(7 downto 0) <= not brytere(7 downto 0);

	key0 <= '1', '0' after 350 ns, '1' after 500 ns;
WAIT;
END PROCESS status_og_brytere;
always : PROCESS
-- optional sensitivity list
-- (        )
-- variable declarations
BEGIN
        -- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END oppg1_SynkOgPuls_arch;