Advertisement
Guest User

Untitled

a guest
Jun 22nd, 2023
48
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 10.08 KB | None | 0 0
  1. /dts-v1/;
  2.  
  3. / {
  4. interrupt-parent = <0x8003>;
  5. model = "linux,dummy-virt";
  6. #size-cells = <0x02>;
  7. #address-cells = <0x02>;
  8. compatible = "linux,dummy-virt";
  9.  
  10. memory@40000000 {
  11. reg = <0x00 0x40000000 0x00 0x80000000>;
  12. device_type = "memory";
  13. };
  14.  
  15. platform-bus@c000000 {
  16. interrupt-parent = <0x8003>;
  17. ranges = <0x00 0x00 0xc000000 0x2000000>;
  18. #address-cells = <0x01>;
  19. #size-cells = <0x01>;
  20. compatible = "qemu,platform\0simple-bus";
  21. };
  22.  
  23. fw-cfg@9020000 {
  24. dma-coherent;
  25. reg = <0x00 0x9020000 0x00 0x18>;
  26. compatible = "qemu,fw-cfg-mmio";
  27. };
  28.  
  29. virtio_mmio@a000000 {
  30. dma-coherent;
  31. interrupts = <0x00 0x10 0x01>;
  32. reg = <0x00 0xa000000 0x00 0x200>;
  33. compatible = "virtio,mmio";
  34. };
  35.  
  36. virtio_mmio@a000200 {
  37. dma-coherent;
  38. interrupts = <0x00 0x11 0x01>;
  39. reg = <0x00 0xa000200 0x00 0x200>;
  40. compatible = "virtio,mmio";
  41. };
  42.  
  43. virtio_mmio@a000400 {
  44. dma-coherent;
  45. interrupts = <0x00 0x12 0x01>;
  46. reg = <0x00 0xa000400 0x00 0x200>;
  47. compatible = "virtio,mmio";
  48. };
  49.  
  50. virtio_mmio@a000600 {
  51. dma-coherent;
  52. interrupts = <0x00 0x13 0x01>;
  53. reg = <0x00 0xa000600 0x00 0x200>;
  54. compatible = "virtio,mmio";
  55. };
  56.  
  57. virtio_mmio@a000800 {
  58. dma-coherent;
  59. interrupts = <0x00 0x14 0x01>;
  60. reg = <0x00 0xa000800 0x00 0x200>;
  61. compatible = "virtio,mmio";
  62. };
  63.  
  64. virtio_mmio@a000a00 {
  65. dma-coherent;
  66. interrupts = <0x00 0x15 0x01>;
  67. reg = <0x00 0xa000a00 0x00 0x200>;
  68. compatible = "virtio,mmio";
  69. };
  70.  
  71. virtio_mmio@a000c00 {
  72. dma-coherent;
  73. interrupts = <0x00 0x16 0x01>;
  74. reg = <0x00 0xa000c00 0x00 0x200>;
  75. compatible = "virtio,mmio";
  76. };
  77.  
  78. virtio_mmio@a000e00 {
  79. dma-coherent;
  80. interrupts = <0x00 0x17 0x01>;
  81. reg = <0x00 0xa000e00 0x00 0x200>;
  82. compatible = "virtio,mmio";
  83. };
  84.  
  85. virtio_mmio@a001000 {
  86. dma-coherent;
  87. interrupts = <0x00 0x18 0x01>;
  88. reg = <0x00 0xa001000 0x00 0x200>;
  89. compatible = "virtio,mmio";
  90. };
  91.  
  92. virtio_mmio@a001200 {
  93. dma-coherent;
  94. interrupts = <0x00 0x19 0x01>;
  95. reg = <0x00 0xa001200 0x00 0x200>;
  96. compatible = "virtio,mmio";
  97. };
  98.  
  99. virtio_mmio@a001400 {
  100. dma-coherent;
  101. interrupts = <0x00 0x1a 0x01>;
  102. reg = <0x00 0xa001400 0x00 0x200>;
  103. compatible = "virtio,mmio";
  104. };
  105.  
  106. virtio_mmio@a001600 {
  107. dma-coherent;
  108. interrupts = <0x00 0x1b 0x01>;
  109. reg = <0x00 0xa001600 0x00 0x200>;
  110. compatible = "virtio,mmio";
  111. };
  112.  
  113. virtio_mmio@a001800 {
  114. dma-coherent;
  115. interrupts = <0x00 0x1c 0x01>;
  116. reg = <0x00 0xa001800 0x00 0x200>;
  117. compatible = "virtio,mmio";
  118. };
  119.  
  120. virtio_mmio@a001a00 {
  121. dma-coherent;
  122. interrupts = <0x00 0x1d 0x01>;
  123. reg = <0x00 0xa001a00 0x00 0x200>;
  124. compatible = "virtio,mmio";
  125. };
  126.  
  127. virtio_mmio@a001c00 {
  128. dma-coherent;
  129. interrupts = <0x00 0x1e 0x01>;
  130. reg = <0x00 0xa001c00 0x00 0x200>;
  131. compatible = "virtio,mmio";
  132. };
  133.  
  134. virtio_mmio@a001e00 {
  135. dma-coherent;
  136. interrupts = <0x00 0x1f 0x01>;
  137. reg = <0x00 0xa001e00 0x00 0x200>;
  138. compatible = "virtio,mmio";
  139. };
  140.  
  141. virtio_mmio@a002000 {
  142. dma-coherent;
  143. interrupts = <0x00 0x20 0x01>;
  144. reg = <0x00 0xa002000 0x00 0x200>;
  145. compatible = "virtio,mmio";
  146. };
  147.  
  148. virtio_mmio@a002200 {
  149. dma-coherent;
  150. interrupts = <0x00 0x21 0x01>;
  151. reg = <0x00 0xa002200 0x00 0x200>;
  152. compatible = "virtio,mmio";
  153. };
  154.  
  155. virtio_mmio@a002400 {
  156. dma-coherent;
  157. interrupts = <0x00 0x22 0x01>;
  158. reg = <0x00 0xa002400 0x00 0x200>;
  159. compatible = "virtio,mmio";
  160. };
  161.  
  162. virtio_mmio@a002600 {
  163. dma-coherent;
  164. interrupts = <0x00 0x23 0x01>;
  165. reg = <0x00 0xa002600 0x00 0x200>;
  166. compatible = "virtio,mmio";
  167. };
  168.  
  169. virtio_mmio@a002800 {
  170. dma-coherent;
  171. interrupts = <0x00 0x24 0x01>;
  172. reg = <0x00 0xa002800 0x00 0x200>;
  173. compatible = "virtio,mmio";
  174. };
  175.  
  176. virtio_mmio@a002a00 {
  177. dma-coherent;
  178. interrupts = <0x00 0x25 0x01>;
  179. reg = <0x00 0xa002a00 0x00 0x200>;
  180. compatible = "virtio,mmio";
  181. };
  182.  
  183. virtio_mmio@a002c00 {
  184. dma-coherent;
  185. interrupts = <0x00 0x26 0x01>;
  186. reg = <0x00 0xa002c00 0x00 0x200>;
  187. compatible = "virtio,mmio";
  188. };
  189.  
  190. virtio_mmio@a002e00 {
  191. dma-coherent;
  192. interrupts = <0x00 0x27 0x01>;
  193. reg = <0x00 0xa002e00 0x00 0x200>;
  194. compatible = "virtio,mmio";
  195. };
  196.  
  197. virtio_mmio@a003000 {
  198. dma-coherent;
  199. interrupts = <0x00 0x28 0x01>;
  200. reg = <0x00 0xa003000 0x00 0x200>;
  201. compatible = "virtio,mmio";
  202. };
  203.  
  204. virtio_mmio@a003200 {
  205. dma-coherent;
  206. interrupts = <0x00 0x29 0x01>;
  207. reg = <0x00 0xa003200 0x00 0x200>;
  208. compatible = "virtio,mmio";
  209. };
  210.  
  211. virtio_mmio@a003400 {
  212. dma-coherent;
  213. interrupts = <0x00 0x2a 0x01>;
  214. reg = <0x00 0xa003400 0x00 0x200>;
  215. compatible = "virtio,mmio";
  216. };
  217.  
  218. virtio_mmio@a003600 {
  219. dma-coherent;
  220. interrupts = <0x00 0x2b 0x01>;
  221. reg = <0x00 0xa003600 0x00 0x200>;
  222. compatible = "virtio,mmio";
  223. };
  224.  
  225. virtio_mmio@a003800 {
  226. dma-coherent;
  227. interrupts = <0x00 0x2c 0x01>;
  228. reg = <0x00 0xa003800 0x00 0x200>;
  229. compatible = "virtio,mmio";
  230. };
  231.  
  232. virtio_mmio@a003a00 {
  233. dma-coherent;
  234. interrupts = <0x00 0x2d 0x01>;
  235. reg = <0x00 0xa003a00 0x00 0x200>;
  236. compatible = "virtio,mmio";
  237. };
  238.  
  239. virtio_mmio@a003c00 {
  240. dma-coherent;
  241. interrupts = <0x00 0x2e 0x01>;
  242. reg = <0x00 0xa003c00 0x00 0x200>;
  243. compatible = "virtio,mmio";
  244. };
  245.  
  246. virtio_mmio@a003e00 {
  247. dma-coherent;
  248. interrupts = <0x00 0x2f 0x01>;
  249. reg = <0x00 0xa003e00 0x00 0x200>;
  250. compatible = "virtio,mmio";
  251. };
  252.  
  253. gpio-restart {
  254. secure-status = "okay";
  255. status = "disabled";
  256. gpios = <0x8005 0x01 0x00>;
  257. compatible = "gpio-restart";
  258. };
  259.  
  260. gpio-poweroff {
  261. secure-status = "okay";
  262. status = "disabled";
  263. gpios = <0x8005 0x00 0x00>;
  264. compatible = "gpio-poweroff";
  265. };
  266.  
  267. pl061@90b0000 {
  268. secure-status = "okay";
  269. status = "disabled";
  270. phandle = <0x8005>;
  271. clock-names = "apb_pclk";
  272. clocks = <0x8000>;
  273. interrupts = <0x00 0x00 0x04>;
  274. gpio-controller;
  275. #gpio-cells = <0x02>;
  276. compatible = "arm,pl061\0arm,primecell";
  277. reg = <0x00 0x90b0000 0x00 0x1000>;
  278. };
  279.  
  280. pcie@10000000 {
  281. interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
  282. interrupt-map = <0x00 0x00 0x00 0x01 0x8003 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x02 0x8003 0x00 0x00 0x00 0x04 0x04 0x00 0x00 0x00 0x03 0x8003 0x00 0x00 0x00 0x05 0x04 0x00 0x00 0x00 0x04 0x8003 0x00 0x00 0x00 0x06 0x04 0x800 0x00 0x00 0x01 0x8003 0x00 0x00 0x00 0x04 0x04 0x800 0x00 0x00 0x02 0x8003 0x00 0x00 0x00 0x05 0x04 0x800 0x00 0x00 0x03 0x8003 0x00 0x00 0x00 0x06 0x04 0x800 0x00 0x00 0x04 0x8003 0x00 0x00 0x00 0x03 0x04 0x1000 0x00 0x00 0x01 0x8003 0x00 0x00 0x00 0x05 0x04 0x1000 0x00 0x00 0x02 0x8003 0x00 0x00 0x00 0x06 0x04 0x1000 0x00 0x00 0x03 0x8003 0x00 0x00 0x00 0x03 0x04 0x1000 0x00 0x00 0x04 0x8003 0x00 0x00 0x00 0x04 0x04 0x1800 0x00 0x00 0x01 0x8003 0x00 0x00 0x00 0x06 0x04 0x1800 0x00 0x00 0x02 0x8003 0x00 0x00 0x00 0x03 0x04 0x1800 0x00 0x00 0x03 0x8003 0x00 0x00 0x00 0x04 0x04 0x1800 0x00 0x00 0x04 0x8003 0x00 0x00 0x00 0x05 0x04>;
  283. #interrupt-cells = <0x01>;
  284. ranges = <0x1000000 0x00 0x00 0x00 0x3eff0000 0x00 0x10000 0x2000000 0x00 0x10000000 0x00 0x10000000 0x00 0x2eff0000 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>;
  285. reg = <0x40 0x10000000 0x00 0x10000000>;
  286. msi-map = <0x00 0x8004 0x00 0x10000>;
  287. dma-coherent;
  288. bus-range = <0x00 0xff>;
  289. linux,pci-domain = <0x00>;
  290. #size-cells = <0x02>;
  291. #address-cells = <0x03>;
  292. device_type = "pci";
  293. compatible = "pci-host-ecam-generic";
  294. };
  295.  
  296. pl031@9010000 {
  297. clock-names = "apb_pclk";
  298. clocks = <0x8000>;
  299. interrupts = <0x00 0x02 0x04>;
  300. reg = <0x00 0x9010000 0x00 0x1000>;
  301. compatible = "arm,pl031\0arm,primecell";
  302. };
  303.  
  304. pl011@9040000 {
  305. secure-status = "okay";
  306. status = "disabled";
  307. clock-names = "uartclk\0apb_pclk";
  308. clocks = <0x8000 0x8000>;
  309. interrupts = <0x00 0x08 0x04>;
  310. reg = <0x00 0x9040000 0x00 0x1000>;
  311. compatible = "arm,pl011\0arm,primecell";
  312. };
  313.  
  314. secram@e000000 {
  315. secure-status = "okay";
  316. status = "disabled";
  317. reg = <0x00 0xe000000 0x00 0x1000000>;
  318. device_type = "memory";
  319. };
  320.  
  321. pl011@9000000 {
  322. clock-names = "uartclk\0apb_pclk";
  323. clocks = <0x8000 0x8000>;
  324. interrupts = <0x00 0x01 0x04>;
  325. reg = <0x00 0x9000000 0x00 0x1000>;
  326. compatible = "arm,pl011\0arm,primecell";
  327. };
  328.  
  329. pmu {
  330. interrupts = <0x01 0x07 0x04>;
  331. compatible = "arm,armv8-pmuv3";
  332. };
  333.  
  334. intc@8000000 {
  335. phandle = <0x8003>;
  336. reg = <0x00 0x8000000 0x00 0x10000 0x00 0x80a0000 0x00 0xf60000>;
  337. #redistributor-regions = <0x01>;
  338. compatible = "arm,gic-v3";
  339. ranges;
  340. #size-cells = <0x02>;
  341. #address-cells = <0x02>;
  342. interrupt-controller;
  343. #interrupt-cells = <0x03>;
  344.  
  345.  
  346. its@8080000 {
  347. phandle = <0x8004>;
  348. reg = <0x00 0x8080000 0x00 0x20000>;
  349. #msi-cells = <0x01>;
  350. msi-controller;
  351. compatible = "arm,gic-v3-its";
  352. };
  353. };
  354.  
  355. flash@4000000 {
  356. bank-width = <0x04>;
  357. reg = <0x00 0x4000000 0x00 0x4000000>;
  358. compatible = "cfi-flash";
  359. };
  360.  
  361. secflash@0 {
  362. secure-status = "okay";
  363. status = "disabled";
  364. bank-width = <0x04>;
  365. reg = <0x00 0x00 0x00 0x4000000>;
  366. compatible = "cfi-flash";
  367. };
  368.  
  369. cpus {
  370. #size-cells = <0x00>;
  371. #address-cells = <0x01>;
  372.  
  373. cpu-map {
  374.  
  375. socket0 {
  376.  
  377. cluster0 {
  378.  
  379. core0 {
  380. cpu = <0x8002>;
  381. };
  382. };
  383. };
  384. };
  385.  
  386. cpu@0 {
  387. phandle = <0x8002>;
  388. reg = <0x00>;
  389. compatible = "arm,cortex-a53";
  390. device_type = "cpu";
  391. enable-method = "psci";
  392. };
  393.  
  394. };
  395.  
  396. timer {
  397. interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>;
  398. always-on;
  399. compatible = "arm,armv8-timer\0arm,armv7-timer";
  400. };
  401.  
  402. apb-pclk {
  403. phandle = <0x8000>;
  404. clock-output-names = "clk24mhz";
  405. clock-frequency = <0x16e3600>;
  406. #clock-cells = <0x00>;
  407. compatible = "fixed-clock";
  408. };
  409.  
  410. secure-chosen {
  411. stdout-path = "/pl011@9040000";
  412. rng-seed = <0x1ad05b2d 0xc9c01d29 0x1759672d 0xf36b819e 0x7dc49aa0 0xa8ff1553 0xb8d23923 0x7f38d9dc>;
  413. kaslr-seed = <0xf14fa021 0x5e668329>;
  414. };
  415.  
  416. psci {
  417. compatible = "arm,psci-1.0";
  418. method = "smc";
  419. };
  420.  
  421. chosen {
  422. bootargs = "console=serial";
  423. stdout-path = "/pl011@9000000";
  424. rng-seed = <0x9e55f29f 0x3c64f6e6 0x5739b378 0xf5fb2be7 0xb10b03a6 0xf466be1d 0xa71ff76f 0x4fde8724>;
  425. kaslr-seed = <0x974499e5 0xe08e9166>;
  426. linux,initrd-start = <0x0>;
  427. linux,initrd-end = <0x0>;
  428. };
  429. };
  430.  
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement