API tools faq
paste
andyp73

libgfxinit monitor not detected

andyp73
Apr 21st, 2021
96
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 99.13 KB | None | 0 0
raw download clone embed print report
  1.  
  2. coreboot-4.13-3181-g1e86675ff0-dirty Fri Apr 16 15:55:59 UTC 2021 bootblock starting (log level: 7)...
  3. CPU: Intel(R) Core(TM) i7-8550U CPU @ 1.80GHz
  4. CPU: ID 806ea, Kabylake Y0, ucode: 000000df
  5. CPU: AES supported, TXT NOT supported, VT supported
  6. MCH: device id 5914 (rev 08) is Kabylake-R ULT
  7. PCH: device id 9d4e (rev 21) is Kabylake-U iHDCP 2.2 Premium
  8. IGD: device id 5917 (rev 07) is Kaby Lake-R ULT GT2
  9. FMAP: Found "FLASH" version 1.1 at 0x270000.
  10. FMAP: base = 0x0 size = 0x800000 #areas = 6
  11. FMAP: area COREBOOT found @ 270200 (5832192 bytes)
  12. CBFS: mcache @0xfef04e00 built for 18 files, used 0x3b8 of 0x2000 bytes
  13. CBFS: Found 'fallback/romstage' @0x80 size 0xd018 in mcache @0xfef04e2c
  14. BS: bootblock times (exec / console): total (unknown) / 68 ms
  15.  
  16.  
  17. coreboot-4.13-3181-g1e86675ff0-dirty Fri Apr 16 15:55:59 UTC 2021 romstage starting (log level: 7)...
  18. pm1_sts: 0000 pm1_en: 4000 pm1_cnt: 00001c00
  19. gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
  20. gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
  21. gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
  22. gpe0_sts[3]: 00010040 gpe0_en[3]: 00000000
  23. TCO_STS: 0000 0000
  24. GEN_PMCON: 60a40200 00005e3a
  25. GBLRST_CAUSE: 00000000 00000000
  26. prev_sleep_state 5
  27. CBFS: Found 'fspm.bin' @0x99dc0 size 0x63000 in mcache @0xfef0506c
  28. FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
  29. SPD index 6
  30. CBFS: Found 'spd.bin' @0x94780 size 0x1000 in mcache @0xfef04fc8
  31. CBMEM:
  32. IMD: root @ 0x7afff000 254 entries.
  33. IMD: root @ 0x7affec00 62 entries.
  34. External stage cache:
  35. IMD: root @ 0x7b3ff000 254 entries.
  36. IMD: root @ 0x7b3fec00 62 entries.
  37. FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
  38. MRC: Checking cached data update for 'RW_MRC_CACHE'.
  39. SF: Detected 00 0000 with sector size 0x1000, total 0x800000
  40. MRC: 'RW_MRC_CACHE' does not need update.
  41. 2 DIMMs found
  42. SMM Memory Map
  43. SMRAM : 0x7b000000 0x800000
  44. Subregion 0: 0x7b000000 0x200000
  45. Subregion 1: 0x7b200000 0x200000
  46. Subregion 2: 0x7b400000 0x400000
  47. top_of_ram = 0x7b000000
  48. MTRR Range: Start=7a000000 End=7b000000 (Size 1000000)
  49. MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
  50. MTRR Range: Start=ff800000 End=0 (Size 800000)
  51. Normal boot
  52. CBFS: Found 'fallback/postcar' @0x121e00 size 0x5048 in mcache @0xfef05114
  53. Loading module at 0x7abd1000 with entry 0x7abd1031. filesize: 0x4d10 memsize: 0x9038
  54. Processing 190 relocs. Offset value of 0x78bd1000
  55. BS: romstage times (exec / console): total (unknown) / 156 ms
  56.  
  57.  
  58. coreboot-4.13-3181-g1e86675ff0-dirty Fri Apr 16 15:55:59 UTC 2021 postcar starting (log level: 7)...
  59. Normal boot
  60. CBFS: Found 'fallback/ramstage' @0x73680 size 0x20b40 in mcache @0x7abfd10c
  61. Loading module at 0x7aaf6000 with entry 0x7aaf6000. filesize: 0x48080 memsize: 0xd9d50
  62. Processing 4522 relocs. Offset value of 0x79cf6000
  63. BS: postcar times (exec / console): total (unknown) / 33 ms
  64.  
  65.  
  66. coreboot-4.13-3181-g1e86675ff0-dirty Fri Apr 16 15:55:59 UTC 2021 ramstage starting (log level: 7)...
  67. Normal boot
  68. ACPI _SWS is PM1 Index -1 GPE Index -1
  69. BS: BS_PRE_DEVICE entry times (exec / console): 0 / 4 ms
  70. CBFS: Found 'cpu_microcode_blob.bin' @0xd140 size 0x66400 in mcache @0x7abfd0ac
  71. microcode: sig=0x806ea pf=0x80 revision=0xdf
  72. Skip microcode update
  73. CBFS: Found 'fsps.bin' @0xfddc0 size 0x23ff2 in mcache @0x7abfd2d4
  74. Detected 4 core, 8 thread CPU.
  75. Setting up SMI for CPU
  76. IED base = 0x7b400000
  77. IED size = 0x00400000
  78. Will perform SMM setup.
  79. CPU: Intel(R) Core(TM) i7-8550U CPU @ 1.80GHz.
  80. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
  81. Processing 16 relocs. Offset value of 0x00030000
  82. Attempting to start 7 APs
  83. Waiting for 10ms after sending INIT.
  84. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1, MCU rev: 0x000000df
  85. done.
  86. AP: slot 4 apic_id 3, MCU rev: 0x000000df
  87. AP: slot 5 apic_id 2, MCU rev: 0x000000df
  88. AP: slot 2 apic_id 7, MCU rev: 0x000000df
  89. AP: slot 3 apic_id 6, MCU rev: 0x000000df
  90. AP: slot 7 apic_id 4, MCU rev: 0x000000df
  91. AP: slot 6 apic_id 5, MCU rev: 0x000000df
  92. Waiting for 2nd SIPI to complete...done.
  93. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
  94. Processing 11 relocs. Offset value of 0x00038000
  95. SMM Module: stub loaded at 0x00038000. Will call 0x7ab1a324
  96. Installing permanent SMM handler to 0x7b000000
  97. Loading module at 0x7b010000 with entry 0x7b010c2a. filesize: 0x31c0 memsize: 0x72a0
  98. Processing 193 relocs. Offset value of 0x7b010000
  99. Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1a0 memsize: 0x1a0
  100. Processing 11 relocs. Offset value of 0x7b008000
  101. SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
  102. SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
  103. SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
  104. SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
  105. SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
  106. SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
  107. SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
  108. SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c2a
  109. Clearing SMI status registers
  110. GPE0 STD STS: LAN_WAKE TCO_SCI
  111. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
  112. In relocation handler: CPU 0
  113. New SMBASE=0x7b000000 IEDBASE=0x7b400000
  114. Writing SMRR. base = 0x7b000006, mask=0xff800800
  115. Relocation complete.
  116. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
  117. In relocation handler: CPU 1
  118. New SMBASE=0x7afffc00 IEDBASE=0x7b400000
  119. Relocation complete.
  120. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
  121. In relocation handler: CPU 7
  122. New SMBASE=0x7affe400 IEDBASE=0x7b400000
  123. Writing SMRR. base = 0x7b000006, mask=0xff800800
  124. Relocation complete.
  125. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
  126. In relocation handler: CPU 6
  127. New SMBASE=0x7affe800 IEDBASE=0x7b400000
  128. Relocation complete.
  129. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
  130. In relocation handler: CPU 2
  131. New SMBASE=0x7afff800 IEDBASE=0x7b400000
  132. Relocation complete.
  133. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
  134. In relocation handler: CPU 3
  135. New SMBASE=0x7afff400 IEDBASE=0x7b400000
  136. Writing SMRR. base = 0x7b000006, mask=0xff800800
  137. Relocation complete.
  138. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
  139. In relocation handler: CPU 4
  140. New SMBASE=0x7afff000 IEDBASE=0x7b400000
  141. Relocation complete.
  142. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
  143. In relocation handler: CPU 5
  144. New SMBASE=0x7affec00 IEDBASE=0x7b400000
  145. Writing SMRR. base = 0x7b000006, mask=0xff800800
  146. Relocation complete.
  147. Initializing CPU #0
  148. CPU: vendor Intel device 806ea
  149. CPU: family 06, model 8e, stepping 0a
  150. Clearing out pending MCEs
  151. Setting up local APIC...
  152. apic_id: 0x00 done.
  153. cpu: energy policy set to 6
  154. Turbo is available but hidden
  155. Turbo is available and visible
  156. Skip microcode update
  157. CPU #0 initialized
  158. Initializing CPU #1
  159. Initializing CPU #6
  160. Initializing CPU #7
  161. CPU: vendor Intel device 806ea
  162. CPU: family 06, model 8e, stepping 0a
  163. CPU: vendor Intel device 806ea
  164. CPU: family 06, model 8e, stepping 0a
  165. Clearing out pending MCEs
  166. Clearing out pending MCEs
  167. Setting up local APIC...
  168. Setting up local APIC...
  169. Initializing CPU #4
  170. Initializing CPU #5
  171. CPU: vendor Intel device 806ea
  172. CPU: family 06, model 8e, stepping 0a
  173. CPU: vendor Intel device 806ea
  174. CPU: family 06, model 8e, stepping 0a
  175. Clearing out pending MCEs
  176. Clearing out pending MCEs
  177. Setting up local APIC...
  178. CPU: vendor Intel device 806ea
  179. CPU: family 06, model 8e, stepping 0a
  180. Clearing out pending MCEs
  181. apic_id: 0x04 done.
  182. apic_id: 0x05 done.
  183. cpu: energy policy set to 6
  184. cpu: energy policy set to 6
  185. Skip microcode update
  186. CPU #7 initialized
  187. Skip microcode update
  188. CPU #6 initialized
  189. Setting up local APIC...
  190. apic_id: 0x02 done.
  191. Setting up local APIC...
  192. apic_id: 0x01 done.
  193. Initializing CPU #2
  194. Initializing CPU #3
  195. CPU: vendor Intel device 806ea
  196. CPU: family 06, model 8e, stepping 0a
  197. CPU: vendor Intel device 806ea
  198. CPU: family 06, model 8e, stepping 0a
  199. Clearing out pending MCEs
  200. Clearing out pending MCEs
  201. Setting up local APIC...
  202. Setting up local APIC...
  203. cpu: energy policy set to 6
  204. apic_id: 0x06 done.
  205. apic_id: 0x07 done.
  206. cpu: energy policy set to 6
  207. cpu: energy policy set to 6
  208. Skip microcode update
  209. CPU #3 initialized
  210. Skip microcode update
  211. CPU #2 initialized
  212. apic_id: 0x03 done.
  213. cpu: energy policy set to 6
  214. cpu: energy policy set to 6
  215. Skip microcode update
  216. CPU #5 initialized
  217. Skip microcode update
  218. CPU #4 initialized
  219. Skip microcode update
  220. CPU #1 initialized
  221. bsp_do_flight_plan done after 444 msecs.
  222. CPU: frequency set to 4000 MHz
  223. Enabling SMIs.
  224. Locking SMM.
  225. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  226. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  227. IA32_FEATURE_CONTROL already locked
  228. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  229. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  230. IA32_FEATURE_CONTROL already locked
  231. IA32_FEATURE_CONTROL already locked
  232. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  233. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  234. IA32_FEATURE_CONTROL already locked
  235. IA32_FEATURE_CONTROL already locked
  236. IA32_FEATURE_CONTROL already locked
  237. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  238. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  239. IA32_FEATURE_CONTROL already locked
  240. IA32_FEATURE_CONTROL already locked
  241. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 400 / 238 ms
  242. gpio_pad_reset_config_override: Logical to Chipset mapping not found
  243. FSPS returned 0
  244. ITSS IRQ Polarities Before:
  245. IPC0: 0x00ff4000
  246. IPC1: 0x00000007
  247. IPC2: 0x00000000
  248. IPC3: 0x00000000
  249. ITSS IRQ Polarities After:
  250. IPC0: 0x00ff4000
  251. IPC1: 0x00000007
  252. IPC2: 0x00000000
  253. IPC3: 0x00000000
  254. Found PCIe Root Port #6 at PCI: 00:1c.0.
  255. Found PCIe Root Port #9 at PCI: 00:1d.0.
  256. Remapping PCIe Root Port #6 from PCI: 00:1c.5 to new function number 0.
  257. BS: BS_DEV_INIT_CHIPS run times (exec / console): 138 / 43 ms
  258. Enumerating buses...
  259. Root Device scanning...
  260. DOMAIN: 0000 enabled
  261. CPU_CLUSTER: 0 enabled
  262. DOMAIN: 0000 scanning...
  263. PCI: pci_scan_bus for bus 00
  264. PCI: 00:00.0 [8086/5914] enabled
  265. PCI: 00:02.0 [8086/5917] enabled
  266. PCI: 00:04.0 [8086/1903] enabled
  267. PCI: 00:14.0 [8086/9d2f] enabled
  268. PCI: 00:14.2 [8086/9d31] enabled
  269. PCI: 00:15.0 [8086/9d60] enabled
  270. PCI: 00:15.1 [8086/9d61] enabled
  271. PCI: 00:15.2 [8086/9d62] disabled
  272. PCI: 00:15.3 [8086/9d63] disabled
  273. PCI: 00:16.0 [8086/9d3a] disabled
  274. PCI: 00:17.0 [8086/9d03] enabled
  275. PCI: 00:19.0 [8086/9d66] enabled
  276. PCI: 00:19.1 [8086/9d65] disabled
  277. PCI: 00:1c.0 [8086/9d15] enabled
  278. PCI: 00:1d.0 [8086/9d18] enabled
  279. PCI: 00:1e.0 [8086/9d27] enabled
  280. PCI: 00:1e.2 [8086/9d29] disabled
  281. PCI: 00:1e.3 [8086/9d2a] disabled
  282. PCI: 00:1f.0 [8086/9d4e] enabled
  283. PCI: 00:1f.1 [8086/9d20] disabled
  284. PCI: 00:1f.2 [8086/9d21] disabled
  285. PCI: 00:1f.3 [8086/9d71] enabled
  286. PCI: 00:1f.4 [8086/9d23] enabled
  287. GPIO: 0 enabled
  288. PCI: Leftover static devices:
  289. PCI: 00:01.0
  290. PCI: 00:01.1
  291. PCI: 00:01.2
  292. PCI: 00:05.0
  293. PCI: 00:07.0
  294. PCI: 00:08.0
  295. PCI: 00:13.0
  296. PCI: 00:14.1
  297. PCI: 00:14.3
  298. PCI: 00:16.1
  299. PCI: 00:16.2
  300. PCI: 00:16.3
  301. PCI: 00:16.4
  302. PCI: 00:19.2
  303. PCI: 00:1b.0
  304. PCI: 00:1b.1
  305. PCI: 00:1b.2
  306. PCI: 00:1b.3
  307. PCI: 00:1b.4
  308. PCI: 00:1b.5
  309. PCI: 00:1b.6
  310. PCI: 00:1b.7
  311. PCI: 00:1d.4
  312. PCI: 00:1d.5
  313. PCI: 00:1d.6
  314. PCI: 00:1d.7
  315. PCI: 00:1e.1
  316. PCI: 00:1e.4
  317. PCI: 00:1e.5
  318. PCI: 00:1e.6
  319. PCI: 00:1f.5
  320. PCI: 00:1f.6
  321. PCI: 00:1f.7
  322. PCI: Check your devicetree.cb.
  323. PCI: 00:02.0 scanning...
  324. scan_bus: bus PCI: 00:02.0 finished in 0 msecs
  325. PCI: 00:14.0 scanning...
  326. scan_bus: bus PCI: 00:14.0 finished in 0 msecs
  327. PCI: 00:15.0 scanning...
  328. I2C: 00:2c enabled
  329. scan_bus: bus PCI: 00:15.0 finished in 1 msecs
  330. PCI: 00:15.1 scanning...
  331. scan_bus: bus PCI: 00:15.1 finished in 0 msecs
  332. PCI: 00:1c.0 scanning...
  333. PCI: pci_scan_bus for bus 01
  334. PCI: 01:00.0 [8086/24fd] enabled
  335. Enabling Common Clock Configuration
  336. L1 Sub-State supported from root port 28
  337. L1 Sub-State Support = 0xf
  338. CommonModeRestoreTime = 0x28
  339. Power On Value = 0x16, Power On Scale = 0x0
  340. ASPM: Enabled L1
  341. PCIe: Max_Payload_Size adjusted to 128
  342. PCI: 01:00.0: Enabled LTR
  343. PCI: 01:00.0: Programmed LTR max latencies
  344. scan_bus: bus PCI: 00:1c.0 finished in 37 msecs
  345. PCI: 00:1d.0 scanning...
  346. PCI: pci_scan_bus for bus 02
  347. PCI: 02:00.0 [1987/5012] enabled
  348. Enabling Common Clock Configuration
  349. PCIE CLK PM is not supported by endpoint
  350. L1 Sub-State supported from root port 29
  351. L1 Sub-State Support = 0xf
  352. CommonModeRestoreTime = 0x28
  353. Power On Value = 0x6, Power On Scale = 0x1
  354. ASPM: Enabled L1
  355. PCIe: Max_Payload_Size adjusted to 128
  356. PCI: 02:00.0: Enabled LTR
  357. PCI: 02:00.0: Programmed LTR max latencies
  358. scan_bus: bus PCI: 00:1d.0 finished in 41 msecs
  359. PCI: 00:1f.0 scanning...
  360. PNP: 004e.0 enabled
  361. scan_bus: bus PCI: 00:1f.0 finished in 2 msecs
  362. PCI: 00:1f.3 scanning...
  363. scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
  364. PCI: 00:1f.4 scanning...
  365. scan_bus: bus PCI: 00:1f.4 finished in 0 msecs
  366. scan_bus: bus DOMAIN: 0000 finished in 279 msecs
  367. scan_bus: bus Root Device finished in 291 msecs
  368. done
  369. BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 299 ms
  370. MRC: Could not find region 'UNIFIED_MRC_CACHE'
  371. FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
  372. MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
  373. BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 14 ms
  374. found VGA at PCI: 00:02.0
  375. Setting up VGA for PCI: 00:02.0
  376. Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  377. Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  378. Allocating resources...
  379. Reading resources...
  380. Done reading resources.
  381. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  382. PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  383. PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  384. PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  385. PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
  386. PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  387. PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  388. PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  389. PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
  390. PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  391. PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  392. PCI: 02:00.0 10 * [0x0 - 0x3fff] mem
  393. PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  394. PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  395. PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  396. === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  397. DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  398. update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  399. update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
  400. DOMAIN: 0000: Resource ranges:
  401. * Base: 1000, Size: dfa0, Tag: 100
  402. * Base: efc0, Size: 1040, Tag: 100
  403. PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
  404. PCI: 00:17.0 20 * [0x1040 - 0x105f] limit: 105f io
  405. PCI: 00:17.0 18 * [0x1060 - 0x1067] limit: 1067 io
  406. PCI: 00:17.0 1c * [0x1068 - 0x106b] limit: 106b io
  407. DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  408. DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
  409. update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
  410. update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
  411. update_constraints: PCI: 00:00.0 02 base fed18000 limit fed18fff mem (fixed)
  412. update_constraints: PCI: 00:00.0 03 base fed19000 limit fed19fff mem (fixed)
  413. update_constraints: PCI: 00:00.0 04 base fed84000 limit fed84fff mem (fixed)
  414. update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
  415. update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
  416. update_constraints: PCI: 00:00.0 07 base fed91000 limit fed91fff mem (fixed)
  417. update_constraints: PCI: 00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
  418. update_constraints: PCI: 00:00.0 09 base 000c0000 limit 7affffff mem (fixed)
  419. update_constraints: PCI: 00:00.0 0a base 7b000000 limit 7fffffff mem (fixed)
  420. update_constraints: PCI: 00:00.0 0b base 100000000 limit 27effffff mem (fixed)
  421. update_constraints: PCI: 00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
  422. update_constraints: PCI: 00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
  423. update_constraints: PCI: 00:19.0 10 base fe030000 limit fe030fff mem (fixed)
  424. DOMAIN: 0000: Resource ranges:
  425. * Base: 80000000, Size: 60000000, Tag: 200
  426. * Base: f0000000, Size: e030000, Tag: 200
  427. * Base: fe031000, Size: cdf000, Tag: 200
  428. * Base: fed1a000, Size: 66000, Tag: 200
  429. * Base: fed85000, Size: b000, Tag: 200
  430. * Base: fed92000, Size: 126e000, Tag: 200
  431. * Base: 27f000000, Size: 7d81000000, Tag: 100200
  432. PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  433. PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
  434. PCI: 00:1c.0 20 * [0x91000000 - 0x910fffff] limit: 910fffff mem
  435. PCI: 00:1d.0 20 * [0x91100000 - 0x911fffff] limit: 911fffff mem
  436. PCI: 00:14.0 10 * [0x91200000 - 0x9120ffff] limit: 9120ffff mem
  437. PCI: 00:1f.3 20 * [0x91210000 - 0x9121ffff] limit: 9121ffff mem
  438. PCI: 00:04.0 10 * [0x91220000 - 0x91227fff] limit: 91227fff mem
  439. PCI: 00:1f.3 10 * [0x91228000 - 0x9122bfff] limit: 9122bfff mem
  440. PCI: 00:17.0 10 * [0x9122c000 - 0x9122dfff] limit: 9122dfff mem
  441. PCI: 00:14.2 10 * [0x9122e000 - 0x9122efff] limit: 9122efff mem
  442. PCI: 00:15.0 10 * [0x9122f000 - 0x9122ffff] limit: 9122ffff mem
  443. PCI: 00:15.1 10 * [0x91230000 - 0x91230fff] limit: 91230fff mem
  444. PCI: 00:19.0 18 * [0x91231000 - 0x91231fff] limit: 91231fff mem
  445. PCI: 00:1e.0 10 * [0x91232000 - 0x91232fff] limit: 91232fff mem
  446. PCI: 00:1e.0 18 * [0x91233000 - 0x91233fff] limit: 91233fff mem
  447. PCI: 00:17.0 24 * [0x91234000 - 0x912347ff] limit: 912347ff mem
  448. PCI: 00:17.0 14 * [0x91235000 - 0x912350ff] limit: 912350ff mem
  449. PCI: 00:1f.4 10 * [0x91236000 - 0x912360ff] limit: 912360ff mem
  450. DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
  451. PCI: 00:1c.0 mem: base: 91000000 size: 100000 align: 20 gran: 20 limit: 910fffff
  452. PCI: 00:1c.0: Resource ranges:
  453. * Base: 91000000, Size: 100000, Tag: 200
  454. PCI: 01:00.0 10 * [0x91000000 - 0x91001fff] limit: 91001fff mem
  455. PCI: 00:1c.0 mem: base: 91000000 size: 100000 align: 20 gran: 20 limit: 910fffff done
  456. PCI: 00:1d.0 mem: base: 91100000 size: 100000 align: 20 gran: 20 limit: 911fffff
  457. PCI: 00:1d.0: Resource ranges:
  458. * Base: 91100000, Size: 100000, Tag: 200
  459. PCI: 02:00.0 10 * [0x91100000 - 0x91103fff] limit: 91103fff mem
  460. PCI: 00:1d.0 mem: base: 91100000 size: 100000 align: 20 gran: 20 limit: 911fffff done
  461. === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  462. PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
  463. PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
  464. PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
  465. PCI: 00:04.0 10 <- [0x0091220000 - 0x0091227fff] size 0x00008000 gran 0x0f mem64
  466. PCI: 00:14.0 10 <- [0x0091200000 - 0x009120ffff] size 0x00010000 gran 0x10 mem64
  467. PCI: 00:14.2 10 <- [0x009122e000 - 0x009122efff] size 0x00001000 gran 0x0c mem64
  468. PCI: 00:15.0 10 <- [0x009122f000 - 0x009122ffff] size 0x00001000 gran 0x0c mem64
  469. PCI: 00:15.1 10 <- [0x0091230000 - 0x0091230fff] size 0x00001000 gran 0x0c mem64
  470. PCI: 00:17.0 10 <- [0x009122c000 - 0x009122dfff] size 0x00002000 gran 0x0d mem
  471. PCI: 00:17.0 14 <- [0x0091235000 - 0x00912350ff] size 0x00000100 gran 0x08 mem
  472. PCI: 00:17.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io
  473. PCI: 00:17.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io
  474. PCI: 00:17.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
  475. PCI: 00:17.0 24 <- [0x0091234000 - 0x00912347ff] size 0x00000800 gran 0x0b mem
  476. PCI: 00:19.0 18 <- [0x0091231000 - 0x0091231fff] size 0x00001000 gran 0x0c mem64
  477. PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
  478. PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  479. PCI: 00:1c.0 20 <- [0x0091000000 - 0x00910fffff] size 0x00100000 gran 0x14 bus 01 mem
  480. PCI: 01:00.0 10 <- [0x0091000000 - 0x0091001fff] size 0x00002000 gran 0x0d mem64
  481. PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
  482. PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
  483. PCI: 00:1d.0 20 <- [0x0091100000 - 0x00911fffff] size 0x00100000 gran 0x14 bus 02 mem
  484. PCI: 02:00.0 10 <- [0x0091100000 - 0x0091103fff] size 0x00004000 gran 0x0e mem64
  485. PCI: 00:1e.0 10 <- [0x0091232000 - 0x0091232fff] size 0x00001000 gran 0x0c mem64
  486. PCI: 00:1e.0 18 <- [0x0091233000 - 0x0091233fff] size 0x00001000 gran 0x0c mem64
  487. PCI: 00:1f.3 10 <- [0x0091228000 - 0x009122bfff] size 0x00004000 gran 0x0e mem64
  488. PCI: 00:1f.3 20 <- [0x0091210000 - 0x009121ffff] size 0x00010000 gran 0x10 mem64
  489. PCI: 00:1f.4 10 <- [0x0091236000 - 0x00912360ff] size 0x00000100 gran 0x08 mem64
  490. Done setting resources.
  491. Done allocating resources.
  492. BS: BS_DEV_RESOURCES run times (exec / console): 2 / 765 ms
  493. Enabling resources...
  494. PCI: 00:00.0 subsystem <- 8086/5914
  495. PCI: 00:00.0 cmd <- 06
  496. PCI: 00:02.0 subsystem <- 8086/5917
  497. PCI: 00:02.0 cmd <- 03
  498. PCI: 00:04.0 subsystem <- 8086/1903
  499. PCI: 00:04.0 cmd <- 02
  500. PCI: 00:14.0 subsystem <- 8086/9d2f
  501. PCI: 00:14.0 cmd <- 02
  502. PCI: 00:14.2 subsystem <- 8086/9d31
  503. PCI: 00:14.2 cmd <- 02
  504. PCI: 00:15.0 subsystem <- 8086/9d60
  505. PCI: 00:15.0 cmd <- 06
  506. PCI: 00:15.1 subsystem <- 8086/9d61
  507. PCI: 00:15.1 cmd <- 06
  508. PCI: 00:17.0 subsystem <- 8086/9d03
  509. PCI: 00:17.0 cmd <- 03
  510. PCI: 00:19.0 subsystem <- 8086/9d66
  511. PCI: 00:19.0 cmd <- 06
  512. PCI: 00:1c.0 bridge ctrl <- 0013
  513. PCI: 00:1c.0 subsystem <- 8086/9d15
  514. PCI: 00:1c.0 cmd <- 06
  515. PCI: 00:1d.0 bridge ctrl <- 0013
  516. PCI: 00:1d.0 subsystem <- 8086/9d18
  517. PCI: 00:1d.0 cmd <- 06
  518. PCI: 00:1e.0 subsystem <- 8086/9d27
  519. PCI: 00:1e.0 cmd <- 02
  520. PCI: 00:1f.0 subsystem <- 8086/9d4e
  521. PCI: 00:1f.0 cmd <- 07
  522. PCI: 00:1f.3 subsystem <- 8086/9d71
  523. PCI: 00:1f.3 cmd <- 02
  524. PCI: 00:1f.4 subsystem <- 8086/9d23
  525. PCI: 00:1f.4 cmd <- 03
  526. PCI: 01:00.0 subsystem <- 8086/24fd
  527. PCI: 01:00.0 cmd <- 02
  528. PCI: 02:00.0 subsystem <- 1987/5012
  529. PCI: 02:00.0 cmd <- 02
  530. done.
  531. BS: BS_DEV_ENABLE run times (exec / console): 1 / 110 ms
  532. HECI: No CSE device
  533. BS: BS_DEV_ENABLE exit times (exec / console): 0 / 2 ms
  534. Initializing devices...
  535. PCI: 00:00.0 init
  536. CPU TDP = 15 Watts
  537. CPU PL1 = 20 Watts
  538. CPU PL2 = 30 Watts
  539. PCI: 00:00.0 init finished in 6 msecs
  540. PCI: 00:02.0 init
  541. CBFS: Found 'vbt.bin' @0x99640 size 0x4a4 in mcache @0x7abfd214
  542. Found a VBT of 6144 bytes after decompression
  543. GMA: Found VBT in CBFS
  544. GMA: Found valid VBT in CBFS
  545. [2.117446] HW.GFX.GMA.Initialize
  546. [2.120549] HW.GFX.GMA.Panel.Setup_PP_Sequencer
  547. [2.125187] HW.GFX.GMA.Panel.Setup_PP_Sequencer
  548. [2.129838] HW.GFX.GMA.Registers.Read: 0x07d001f4 <- 0x000c7208:PCH_PP_ON_DELAYS
  549. [2.137765] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  550. [2.145792] HW.GFX.GMA.Registers.Read: 0x0004af06 <- 0x000c7210:PCH_PP_DIVISOR
  551. [2.153516] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS
  552. [2.160293] HW.GFX.GMA.Registers.Read: 0x07d001f4 <- 0x000c7208:PCH_PP_ON_DELAYS
  553. [2.168211] HW.GFX.GMA.Registers.Write: 0x07d00001 -> 0x000c7208:PCH_PP_ON_DELAYS
  554. [2.176149] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS
  555. [2.183015] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  556. [2.191031] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS
  557. [2.199067] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR
  558. [2.205642] HW.GFX.GMA.Registers.Read: 0x0004af06 <- 0x000c7210:PCH_PP_DIVISOR
  559. [2.213367] HW.GFX.GMA.Registers.Write: 0x0004af06 -> 0x000c7210:PCH_PP_DIVISOR
  560. [2.221110] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL
  561. [2.228072] HW.GFX.GMA.Registers.Read: 0x00000008 <- 0x000c7204:PCH_PP_CONTROL
  562. [2.235797] HW.GFX.GMA.Registers.Write: 0x0000000a -> 0x000c7204:PCH_PP_CONTROL
  563. [2.243542] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  564. [2.249333] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  565. [2.256970] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  566. [2.263361] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL
  567. [2.270893] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL
  568. [2.278445] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  569. [2.284051] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP
  570. [2.291487] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  571. [2.297879] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL
  572. [2.305409] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL
  573. [2.312961] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  574. [2.318570] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP
  575. [2.326005] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  576. [2.332396] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL
  577. [2.339929] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL
  578. [2.347479] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e00:DDI_BUF_TRANS_A_S0T1
  579. [2.355786] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2
  580. [2.364102] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1
  581. [2.372417] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2
  582. [2.380732] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1
  583. [2.389047] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e14:DDI_BUF_TRANS_A_S2T2
  584. [2.397361] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1
  585. [2.405676] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2
  586. [2.413992] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e20:DDI_BUF_TRANS_A_S4T1
  587. [2.422309] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e24:DDI_BUF_TRANS_A_S4T2
  588. [2.430625] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1
  589. [2.438941] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2
  590. [2.447256] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1
  591. [2.455569] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2
  592. [2.463886] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1
  593. [2.472200] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2
  594. [2.480515] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1
  595. [2.488828] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2
  596. [2.497145] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1
  597. [2.505460] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2
  598. [2.513773] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e60:DDI_BUF_TRANS_B_S0T1
  599. [2.522089] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2
  600. [2.530405] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1
  601. [2.538718] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2
  602. [2.547033] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1
  603. [2.555348] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e74:DDI_BUF_TRANS_B_S2T2
  604. [2.563664] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1
  605. [2.571979] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2
  606. [2.580295] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e80:DDI_BUF_TRANS_B_S4T1
  607. [2.588610] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e84:DDI_BUF_TRANS_B_S4T2
  608. [2.596926] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1
  609. [2.605242] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2
  610. [2.613558] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1
  611. [2.621874] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2
  612. [2.630188] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1
  613. [2.638505] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2
  614. [2.646819] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1
  615. [2.655135] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2
  616. [2.663451] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1
  617. [2.671766] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2
  618. [2.680081] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1
  619. [2.688398] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2
  620. [2.696713] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1
  621. [2.705026] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2
  622. [2.713341] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1
  623. [2.721656] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2
  624. [2.729971] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1
  625. [2.738288] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2
  626. [2.746602] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1
  627. [2.754917] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2
  628. [2.763232] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1
  629. [2.771549] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2
  630. [2.779865] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1
  631. [2.788179] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2
  632. [2.796492] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1
  633. [2.804808] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064efc:DDI_BUF_TRANS_C_S7T2
  634. [2.813124] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1
  635. [2.821439] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2
  636. [2.829753] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1
  637. [2.838068] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2
  638. [2.846384] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0
  639. [2.853539] HW.GFX.GMA.Registers.Read: 0x0036db00 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  640. [2.861855] HW.GFX.GMA.Registers.Write: 0x0036db00 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  641. [2.870273] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
  642. [2.876889] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL
  643. [2.884430] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
  644. [2.891972] HW.GFX.GMA.Registers.Set_Mask: 0x000f8000 .S DPLL_CTRL2
  645. [2.898549] HW.GFX.GMA.Registers.Read: 0x00af8003 <- 0x0006c05c:DPLL_CTRL2
  646. [2.905896] HW.GFX.GMA.Registers.Write: 0x00af8003 -> 0x0006c05c:DPLL_CTRL2
  647. [2.913244] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT
  648. [2.920205] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT
  649. [2.927938] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT
  650. [2.935674] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS
  651. [2.944377] HW.GFX.GMA.Power_And_Clocks.PD_On
  652. [2.948825] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  653. [2.956850] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  654. [2.965070] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  655. [2.973095] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  656. [2.981216] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  657. [2.988856] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  658. [2.996495] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER
  659. [3.003941] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  660. [3.012161] HW.GFX.GMA.Registers.Write: 0x70000001 -> 0x00045404:PWR_WELL_CTL_DRIVER
  661. [3.020379] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  662. [3.029855] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS
  663. [3.038557] HW.GFX.GMA.Power_And_Clocks.PD_On
  664. [3.043005] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  665. [3.051030] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  666. [3.059249] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  667. [3.067274] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  668. [3.075397] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  669. [3.083037] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  670. [3.090676] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER
  671. [3.098121] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  672. [3.106341] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  673. [3.114561] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER
  674. [3.124040] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL
  675. [3.130614] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL
  676. [3.137963] HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL
  677. [3.145312] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL
  678. [3.153918] HW.GFX.GMA.Registers.Read: 0x0c000544 <- 0x00046000:CDCLK_CTL
  679. [3.161169] HW.GFX.GMA.Registers.Read: 0x20400042 <- 0x00051000:DFSM
  680. [3.167938] HW.GFX.GMA.PCode.Mailbox_Write_Read
  681. [3.172580] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  682. [3.181186] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  683. [3.189018] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  684. [3.197043] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  685. [3.204392] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  686. [3.212998] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
  687. [3.220829] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1
  688. [3.228854] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  689. [3.236686] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  690. [3.244711] HW.GFX.GMA.PCode.Mailbox_Write_Read
  691. [3.249353] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  692. [3.257184] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  693. [3.265210] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  694. [3.272557] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  695. [3.281164] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA
  696. [3.288993] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1
  697. [3.297019] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  698. [3.304850] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  699. [3.312876] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL
  700. [3.320128] HW.GFX.GMA.PCode.Mailbox_Write_Read
  701. [3.324770] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  702. [3.332604] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  703. [3.340629] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  704. [3.347978] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL
  705. [3.354358] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL
  706. [3.361513] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL
  707. [3.368668] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL
  708. [3.377081] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
  709. [3.383764] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ
  710. [3.391586] HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ
  711. [3.399427] HW.GFX.GMA.Panel.On
  712. [3.402512] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  713. [3.408419] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
  714. [3.416144] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  715. [3.423114] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
  716. [3.430841] HW.GFX.GMA.Registers.Write: 0x0000000b -> 0x000c7204:PCH_PP_CONTROL
  717. [3.438586] HW.GFX.GMA.Display_Probing.Read_EDID
  718. [3.443315] HW.GFX.GMA.Power_And_Clocks.PD_On
  719. [3.447764] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  720. [3.455789] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  721. [3.464010] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  722. [3.472037] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  723. [3.480158] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  724. [3.487798] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  725. [3.495437] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER
  726. [3.502884] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  727. [3.511102] HW.GFX.GMA.Registers.Write: 0xf0000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  728. [3.519319] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  729. [3.528795] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS
  730. [3.537500] HW.GFX.GMA.Power_And_Clocks.PD_On
  731. [3.541947] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  732. [3.549973] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  733. [3.558193] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  734. [3.566220] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  735. [3.574344] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  736. [3.581984] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  737. [3.589624] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  738. [3.599103] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER
  739. [3.606550] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  740. [3.614770] HW.GFX.GMA.Registers.Write: 0xf0000023 -> 0x00045404:PWR_WELL_CTL_DRIVER
  741. [3.622990] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  742. [3.632468] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  743. [3.638268] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  744. [3.645907] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  745. [3.653836] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  746. [3.660316] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  747. [3.667956] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  748. [3.675595] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  749. [3.684495] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  750. [3.692132] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  751. [3.697936] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  752. [3.705576] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  753. [3.713505] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  754. [3.719986] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  755. [3.727624] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  756. [3.735263] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  757. [3.744161] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  758. [3.751800] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  759. [3.757604] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  760. [3.765242] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  761. [3.773175] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  762. [3.779655] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  763. [3.787294] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  764. [3.794936] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  765. [3.803835] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  766. [3.811474] HW.GFX.GMA.Display_Probing.Read_EDID
  767. [3.816212] HW.GFX.GMA.I2C.I2C_Read
  768. [3.819694] HW.GFX.GMA.I2C.Init_GMBUS
  769. [3.823370] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
  770. [3.830633] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  771. [3.838651] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  772. [3.846688] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
  773. [3.855297] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
  774. [3.862645] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
  775. [3.869995] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
  776. [3.877345] HW.GFX.GMA.I2C.Check_And_Reset
  777. [3.881503] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
  778. [3.888844] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
  779. [3.896203] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
  780. [3.904818] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
  781. [3.912148] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
  782. [3.920767] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
  783. [3.928116] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
  784. [3.935465] HW.GFX.GMA.I2C.Release_GMBUS
  785. [3.939420] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
  786. [3.946780] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
  787. [3.954131] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
  788. [3.961578] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  789. [3.969594] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  790. [3.977631] HW.GFX.GMA.Display_Probing.Read_EDID
  791. [3.982359] HW.GFX.GMA.I2C.I2C_Read
  792. [3.985841] HW.GFX.GMA.I2C.Init_GMBUS
  793. [3.989516] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
  794. [3.996779] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  795. [4.004794] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  796. [4.012829] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
  797. [4.021437] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
  798. [4.028785] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
  799. [4.036135] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0
  800. [4.043483] HW.GFX.GMA.I2C.Check_And_Reset
  801. [4.047642] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
  802. [4.054981] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
  803. [4.062341] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
  804. [4.570948] HW.GFX.GMA.Registers.Wait: Timed Out!
  805. [4.575603] HW.GFX.GMA.Registers.Read: 0x00008200 <- 0x000c5108:PCH_GMBUS2
  806. [4.582945] HW.GFX.GMA.I2C.Release_GMBUS
  807. [4.586910] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
  808. [4.594270] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
  809. [4.601620] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
  810. [4.609066] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  811. [4.617082] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  812. [4.625121] HW.GFX.GMA.Panel.Wait_On
  813. [4.628689] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  814. [4.637598] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  815. [4.644755] HW.GFX.GMA.Registers.Read: 0x0000000b <- 0x000c7204:PCH_PP_CONTROL
  816. [4.652482] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  817. [4.660229] HW.GFX.GMA.Display_Probing.Read_EDID
  818. [4.664960] HW.GFX.GMA.Power_And_Clocks.PD_On
  819. [4.669408] HW.GFX.GMA.Registers.Read: 0xf0000013 <- 0x00045400:PWR_WELL_CTL_BIOS
  820. [4.677436] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
  821. [4.685659] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  822. [4.693688] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  823. [4.701812] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  824. [4.709455] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  825. [4.717097] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  826. [4.726573] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  827. [4.734022] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
  828. [4.742244] HW.GFX.GMA.Registers.Write: 0xf000003b -> 0x00045404:PWR_WELL_CTL_DRIVER
  829. [4.750466] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  830. [4.759946] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  831. [4.765749] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  832. [4.773390] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  833. [4.781322] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  834. [4.787802] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  835. [4.795444] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  836. [4.803086] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  837. [4.811987] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  838. [4.819630] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  839. [4.827561] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  840. [4.833366] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  841. [4.841008] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  842. [4.848941] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  843. [4.856874] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  844. [4.863353] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  845. [4.870996] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  846. [4.878638] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  847. [4.887539] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  848. [4.895180] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  849. [4.903113] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  850. [4.908916] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  851. [4.916558] HW.GFX.GMA.Registers.Write: 0x00005000 -> 0x00064014:DDI_AUX_DATA_A_1
  852. [4.924491] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  853. [4.930971] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  854. [4.938613] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  855. [4.946255] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  856. [4.955158] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  857. [4.962800] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  858. [4.970731] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  859. [4.976535] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  860. [4.984178] HW.GFX.GMA.Registers.Write: 0x50005000 -> 0x00064014:DDI_AUX_DATA_A_1
  861. [4.992109] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  862. [4.998592] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  863. [5.006233] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  864. [5.013876] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  865. [5.022776] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  866. [5.030418] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  867. [5.038350] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  868. [5.044155] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  869. [5.051798] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  870. [5.059731] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  871. [5.066212] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  872. [5.073854] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  873. [5.081496] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  874. [5.090398] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  875. [5.098041] HW.GFX.GMA.Registers.Read: 0x0000ffff <- 0x00064014:DDI_AUX_DATA_A_1
  876. [5.105972] HW.GFX.GMA.Registers.Read: 0xffffffff <- 0x00064018:DDI_AUX_DATA_A_2
  877. [5.113904] HW.GFX.GMA.Registers.Read: 0x00387015 <- 0x0006401c:DDI_AUX_DATA_A_3
  878. [5.121838] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4
  879. [5.129769] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  880. [5.137703] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  881. [5.143506] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  882. [5.151146] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  883. [5.159079] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  884. [5.165560] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  885. [5.173201] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  886. [5.180843] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  887. [5.189746] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  888. [5.197387] HW.GFX.GMA.Registers.Read: 0x00001a01 <- 0x00064014:DDI_AUX_DATA_A_1
  889. [5.205318] HW.GFX.GMA.Registers.Read: 0x04a51d11 <- 0x00064018:DDI_AUX_DATA_A_2
  890. [5.213253] HW.GFX.GMA.Registers.Read: 0x7806ee95 <- 0x0006401c:DDI_AUX_DATA_A_3
  891. [5.221185] HW.GFX.GMA.Registers.Read: 0xa3544c99 <- 0x00064020:DDI_AUX_DATA_A_4
  892. [5.229117] HW.GFX.GMA.Registers.Read: 0x26000000 <- 0x00064024:DDI_AUX_DATA_A_5
  893. [5.237049] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  894. [5.242854] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  895. [5.250497] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  896. [5.258430] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  897. [5.264911] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  898. [5.272555] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  899. [5.280198] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  900. [5.289099] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  901. [5.296739] HW.GFX.GMA.Registers.Read: 0x000f5054 <- 0x00064014:DDI_AUX_DATA_A_1
  902. [5.304673] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00064018:DDI_AUX_DATA_A_2
  903. [5.312605] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x0006401c:DDI_AUX_DATA_A_3
  904. [5.320539] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x00064020:DDI_AUX_DATA_A_4
  905. [5.328470] HW.GFX.GMA.Registers.Read: 0x01000000 <- 0x00064024:DDI_AUX_DATA_A_5
  906. [5.336402] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  907. [5.342207] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  908. [5.349850] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  909. [5.357782] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  910. [5.364265] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  911. [5.371905] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  912. [5.379549] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  913. [5.388450] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  914. [5.396091] HW.GFX.GMA.Registers.Read: 0x00010101 <- 0x00064014:DDI_AUX_DATA_A_1
  915. [5.404025] HW.GFX.GMA.Registers.Read: 0x0101011a <- 0x00064018:DDI_AUX_DATA_A_2
  916. [5.411956] HW.GFX.GMA.Registers.Read: 0x3680a070 <- 0x0006401c:DDI_AUX_DATA_A_3
  917. [5.419890] HW.GFX.GMA.Registers.Read: 0x381f4030 <- 0x00064020:DDI_AUX_DATA_A_4
  918. [5.427821] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064024:DDI_AUX_DATA_A_5
  919. [5.435755] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  920. [5.441560] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  921. [5.449202] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  922. [5.457135] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  923. [5.463617] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  924. [5.471259] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  925. [5.478903] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  926. [5.487803] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  927. [5.495446] HW.GFX.GMA.Registers.Read: 0x00350026 <- 0x00064014:DDI_AUX_DATA_A_1
  928. [5.503379] HW.GFX.GMA.Registers.Read: 0xa5100000 <- 0x00064018:DDI_AUX_DATA_A_2
  929. [5.511312] HW.GFX.GMA.Registers.Read: 0x18542b80 <- 0x0006401c:DDI_AUX_DATA_A_3
  930. [5.519243] HW.GFX.GMA.Registers.Read: 0xa070381f <- 0x00064020:DDI_AUX_DATA_A_4
  931. [5.527179] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00064024:DDI_AUX_DATA_A_5
  932. [5.535112] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  933. [5.540915] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  934. [5.548558] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  935. [5.556493] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  936. [5.562975] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  937. [5.570616] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  938. [5.578260] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  939. [5.587162] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  940. [5.594804] HW.GFX.GMA.Registers.Read: 0x00302035 <- 0x00064014:DDI_AUX_DATA_A_1
  941. [5.602735] HW.GFX.GMA.Registers.Read: 0x0026a510 <- 0x00064018:DDI_AUX_DATA_A_2
  942. [5.610669] HW.GFX.GMA.Registers.Read: 0x00001800 <- 0x0006401c:DDI_AUX_DATA_A_3
  943. [5.618601] HW.GFX.GMA.Registers.Read: 0x00001000 <- 0x00064020:DDI_AUX_DATA_A_4
  944. [5.626533] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  945. [5.634465] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  946. [5.640270] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  947. [5.647912] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  948. [5.655845] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  949. [5.662325] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  950. [5.669968] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  951. [5.677610] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  952. [5.686511] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  953. [5.694153] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  954. [5.702084] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064018:DDI_AUX_DATA_A_2
  955. [5.710017] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006401c:DDI_AUX_DATA_A_3
  956. [5.717950] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4
  957. [5.725882] HW.GFX.GMA.Registers.Read: 0xfc000000 <- 0x00064024:DDI_AUX_DATA_A_5
  958. [5.733815] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  959. [5.739620] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  960. [5.747262] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  961. [5.755195] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  962. [5.761676] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  963. [5.769317] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  964. [5.776959] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  965. [5.785860] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  966. [5.793503] HW.GFX.GMA.Registers.Read: 0x00004c43 <- 0x00064014:DDI_AUX_DATA_A_1
  967. [5.801435] HW.GFX.GMA.Registers.Read: 0x3133334c <- 0x00064018:DDI_AUX_DATA_A_2
  968. [5.809367] HW.GFX.GMA.Registers.Read: 0x46324c30 <- 0x0006401c:DDI_AUX_DATA_A_3
  969. [5.817300] HW.GFX.GMA.Registers.Read: 0x330a2000 <- 0x00064020:DDI_AUX_DATA_A_4
  970. [5.825232] HW.GFX.GMA.Registers.Read: 0xb5000000 <- 0x00064024:DDI_AUX_DATA_A_5
  971. [5.833165] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  972. [5.838969] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  973. [5.846610] HW.GFX.GMA.Registers.Write: 0x10005000 -> 0x00064014:DDI_AUX_DATA_A_1
  974. [5.854543] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  975. [5.861025] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  976. [5.868667] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  977. [5.876309] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  978. [5.885210] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  979. [5.892851] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  980. [5.900783] EDID+0x0000: 00 ff ff ff ff ff ff 00 38 70 15 00 00 00 00 00
  981. [5.908137] EDID+0x0010: 00 1a 01 04 a5 1d 11 78 06 ee 95 a3 54 4c 99 26
  982. [5.915490] EDID+0x0020: 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
  983. [5.922843] EDID+0x0030: 01 01 01 01 01 01 1a 36 80 a0 70 38 1f 40 30 20
  984. [5.930194] EDID+0x0040: 35 00 26 a5 10 00 00 18 54 2b 80 a0 70 38 1f 40
  985. [5.937546] EDID+0x0050: 30 20 35 00 26 a5 10 00 00 18 00 00 00 10 00 00
  986. [5.944899] EDID+0x0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc
  987. [5.952250] EDID+0x0070: 00 4c 43 31 33 33 4c 46 32 4c 30 33 0a 20 00 b5
  988. [5.959603] HW.GFX.GMA.Power_And_Clocks.PD_Off
  989. [5.964150] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  990. [5.972181] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  991. [5.980405] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  992. [5.988434] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  993. [5.996559] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  994. [6.004202] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  995. [6.011844] HW.GFX.GMA.Power_And_Clocks.PD_Off
  996. [6.016391] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  997. [6.024420] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  998. [6.032643] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  999. [6.040671] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1000. [6.048799] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1001. [6.056440] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1002. [6.064081] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1003. [6.068628] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  1004. [6.076658] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1005. [6.084882] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1006. [6.092910] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1007. [6.101036] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1008. [6.108678] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1009. [6.116319] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  1010. [6.125802] HW.GFX.GMA.Registers.Unset_Mask: 0x00000020 !S PWR_WELL_CTL_DRIVER
  1011. [6.133444] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1012. [6.141666] HW.GFX.GMA.Registers.Write: 0xf000001f -> 0x00045404:PWR_WELL_CTL_DRIVER
  1013. [6.149887] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1014. [6.154434] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  1015. [6.162463] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1016. [6.170687] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1017. [6.178715] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1018. [6.186842] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1019. [6.194483] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1020. [6.202123] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1021. [6.211604] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER
  1022. [6.219246] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1023. [6.227469] HW.GFX.GMA.Registers.Write: 0xf0000007 -> 0x00045404:PWR_WELL_CTL_DRIVER
  1024. [6.235691] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1025. [6.240239] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1026. [6.248266] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1027. [6.256491] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1028. [6.264520] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1029. [6.272645] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1030. [6.280287] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1031. [6.287929] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  1032. [6.297411] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_BIOS
  1033. [6.304859] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1034. [6.312887] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045400:PWR_WELL_CTL_BIOS
  1035. [6.320916] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_DRIVER
  1036. [6.328559] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1037. [6.336782] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  1038.  
  1039. [6.345199] CONFIG =>
  1040. [6.347325] (Primary =>
  1041. [6.350034] (Port => eDP ,
  1042. [6.353516] Framebuffer =>
  1043. [6.356708] (Width => 1920,
  1044. [6.360577] Height => 1080,
  1045. [6.364447] Start_X => 0,
  1046. [6.368027] Start_Y => 0,
  1047. [6.371605] Stride => 1920,
  1048. [6.375473] V_Stride => 1080,
  1049. [6.379342] Tiling => Linear ,
  1050. [6.383502] Rotation => No_Rotation,
  1051. [6.388049] Offset => 0x00000000,
  1052. [6.392207] BPC => 8),
  1053. [6.395592] Mode =>
  1054. [6.398108] (Dotclock => 138500000,
  1055. [6.403332] H_Visible => 1920,
  1056. [6.408072] H_Sync_Begin => 1968,
  1057. [6.412811] H_Sync_End => 2000,
  1058. [6.417551] H_Total => 2080,
  1059. [6.422289] V_Visible => 1080,
  1060. [6.427028] V_Sync_Begin => 1083,
  1061. [6.431769] V_Sync_End => 1088,
  1062. [6.436508] V_Total => 1111,
  1063. [6.441247] H_Sync_Active_High => False,
  1064. [6.446083] V_Sync_Active_High => False,
  1065. [6.450918] BPC => 8)),
  1066. [6.455560] Secondary =>
  1067. [6.458268] (Port => Disabled,
  1068. [6.461750] Framebuffer =>
  1069. [6.464942] (Width => 1,
  1070. [6.468521] Height => 1,
  1071. [6.472098] Start_X => 0,
  1072. [6.475676] Start_Y => 0,
  1073. [6.479256] Stride => 1,
  1074. [6.482833] V_Stride => 1,
  1075. [6.486410] Tiling => Linear ,
  1076. [6.490570] Rotation => No_Rotation,
  1077. [6.495117] Offset => 0x00000000,
  1078. [6.499277] BPC => 8),
  1079. [6.502662] Mode =>
  1080. [6.505178] (Dotclock => 1000000,
  1081. [6.510208] H_Visible => 1,
  1082. [6.514657] H_Sync_Begin => 1,
  1083. [6.519106] H_Sync_End => 1,
  1084. [6.523554] H_Total => 1,
  1085. [6.528005] V_Visible => 1,
  1086. [6.532455] V_Sync_Begin => 1,
  1087. [6.536903] V_Sync_End => 1,
  1088. [6.541354] V_Total => 1,
  1089. [6.545804] H_Sync_Active_High => False,
  1090. [6.550641] V_Sync_Active_High => False,
  1091. [6.555477] BPC => 5)),
  1092. [6.560120] Tertiary =>
  1093. [6.562828] (Port => Disabled,
  1094. [6.566309] Framebuffer =>
  1095. [6.569501] (Width => 1,
  1096. [6.573081] Height => 1,
  1097. [6.576659] Start_X => 0,
  1098. [6.580238] Start_Y => 0,
  1099. [6.583818] Stride => 1,
  1100. [6.587398] V_Stride => 1,
  1101. [6.590976] Tiling => Linear ,
  1102. [6.595135] Rotation => No_Rotation,
  1103. [6.599682] Offset => 0x00000000,
  1104. [6.603841] BPC => 8),
  1105. [6.607227] Mode =>
  1106. [6.609740] (Dotclock => 1000000,
  1107. [6.614771] H_Visible => 1,
  1108. [6.619221] H_Sync_Begin => 1,
  1109. [6.623671] H_Sync_End => 1,
  1110. [6.628120] H_Total => 1,
  1111. [6.632570] V_Visible => 1,
  1112. [6.637019] V_Sync_Begin => 1,
  1113. [6.641469] V_Sync_End => 1,
  1114. [6.645919] V_Total => 1,
  1115. [6.650368] H_Sync_Active_High => False,
  1116. [6.655206] V_Sync_Active_High => False,
  1117. [6.660042] BPC => 5)));
  1118. [6.803153] HW.GFX.GMA.Power_And_Clocks.PD_On
  1119. [6.807419] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1120. [6.815448] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1121. [6.823670] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1122. [6.831699] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1123. [6.839825] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1124. [6.847469] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1125. [6.855111] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1126. [6.864591] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  1127. [6.872040] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1128. [6.880262] HW.GFX.GMA.Registers.Write: 0x3000000b -> 0x00045404:PWR_WELL_CTL_DRIVER
  1129. [6.888486] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1130.  
  1131. [6.898159] Trying to enable port eDP
  1132. [6.902320] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting
  1133. [6.908220] HW.GFX.GMA.Panel.On
  1134. [6.911316] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  1135. [6.917226] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1136. [6.924955] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  1137. [6.931930] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1138. [6.939660] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  1139. [6.947408] HW.GFX.GMA.Panel.Wait_On
  1140. [6.950979] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  1141. [6.959889] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  1142. [6.967047] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1143. [6.974776] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  1144. [6.982526] HW.GFX.GMA.DP_Info.Read_Caps
  1145. [6.986483] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1146. [6.992286] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1147. [6.999929] HW.GFX.GMA.Registers.Write: 0x9000000e -> 0x00064014:DDI_AUX_DATA_A_1
  1148. [7.007862] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1149. [7.014345] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1150. [7.021987] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1151. [7.029629] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1152. [7.038530] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1153. [7.046171] HW.GFX.GMA.Registers.Read: 0x00120a02 <- 0x00064014:DDI_AUX_DATA_A_1
  1154. [7.054104] HW.GFX.GMA.Registers.Read: 0x41000001 <- 0x00064018:DDI_AUX_DATA_A_2
  1155. [7.062036] HW.GFX.GMA.Registers.Read: 0x80020000 <- 0x0006401c:DDI_AUX_DATA_A_3
  1156. [7.069967] HW.GFX.GMA.Registers.Read: 0x00000b00 <- 0x00064020:DDI_AUX_DATA_A_4
  1157.  
  1158. [7.078095] DPCD:
  1159. [7.079835] Rev : 0x12
  1160. [7.083415] Max_Link_Rate : 0x0a
  1161. [7.086994] Max_Lane_Count : 0x02
  1162. [7.090574] TPS3_Supported : 0x00
  1163. [7.094153] Enhanced_Framing: 0x00
  1164. [7.097732] No_Aux_Handshake: 0x40
  1165. [7.101311] Aux_RD_Interval : 0x00
  1166.  
  1167. [7.105084] HW.GFX.GMA.DP_Info.Read_eDP_Rates
  1168. [7.109533] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1169. [7.115337] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1170. [7.122981] HW.GFX.GMA.Registers.Write: 0x90070002 -> 0x00064014:DDI_AUX_DATA_A_1
  1171. [7.130914] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1172. [7.137395] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1173. [7.145037] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1174. [7.152680] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1175. [7.161580] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1176. [7.169221] HW.GFX.GMA.Registers.Read: 0x00011800 <- 0x00064014:DDI_AUX_DATA_A_1
  1177. [7.177155] Trying DP settings: Symbol Rate = 270000000; Lane Count = 2
  1178.  
  1179. [7.184314] HW.GFX.GMA.PLLs.Alloc
  1180. [7.187603] HW.GFX.GMA.Registers.Read: 0x000000c5 <- 0x0006c058:DPLL_CTRL1
  1181. [7.194956] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1
  1182. [7.201146] HW.GFX.GMA.Registers.Read: 0x000000c5 <- 0x0006c058:DPLL_CTRL1
  1183. [7.208498] HW.GFX.GMA.Registers.Write: 0x000000c5 -> 0x0006c058:DPLL_CTRL1
  1184. [7.215851] HW.GFX.GMA.Registers.Read: 0x000000c5 <- 0x0006c058:DPLL_CTRL1
  1185. [7.223203] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL
  1186. [7.230556] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS
  1187. [7.239271] HW.GFX.GMA.Connectors.Pre_On
  1188. [7.243223] HW.GFX.GMA.Connectors.DDI.Pre_On
  1189. [7.247574] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2
  1190. [7.253766] HW.GFX.GMA.Registers.Read: 0x00af8003 <- 0x0006c05c:DPLL_CTRL2
  1191. [7.261114] HW.GFX.GMA.Registers.Write: 0x00af0003 -> 0x0006c05c:DPLL_CTRL2
  1192. [7.268464] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP
  1193. [7.274558] HW.GFX.GMA.Registers.Write: 0x80000080 -> 0x00064040:DP_TP_CTL_A
  1194. [7.282007] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1195. [7.287812] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1196. [7.295450] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1197. [7.301930] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1198. [7.309569] HW.GFX.GMA.Registers.Write: 0x80000093 -> 0x00064000:DDI_BUF_CTL_A
  1199. [7.317211] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A
  1200. [7.325450] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init
  1201. [7.331446] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1202. [7.337249] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1203. [7.344888] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064014:DDI_AUX_DATA_A_1
  1204. [7.352819] HW.GFX.GMA.Registers.Write: 0x0a020000 -> 0x00064018:DDI_AUX_DATA_A_2
  1205. [7.360751] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1206. [7.367232] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1207. [7.374873] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1208. [7.382513] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1209. [7.391410] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1210. [7.399049] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1211. [7.406981] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1212. [7.412782] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1213. [7.420423] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064014:DDI_AUX_DATA_A_1
  1214. [7.428356] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1215. [7.436286] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1216. [7.442766] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1217. [7.450408] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1218. [7.458050] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1219. [7.466952] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1220. [7.474591] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1221. [7.482521] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1222. [7.490258] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1223. [7.496060] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1224. [7.503700] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1225. [7.511630] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1226. [7.519563] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1227. [7.526043] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1228. [7.533685] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1229. [7.541326] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1230. [7.550224] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1231. [7.557863] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1232. [7.565893] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1233. [7.572996] HW.GFX.GMA.DP_Info.Read_Link_Status
  1234. [7.577639] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1235. [7.583441] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1236. [7.591083] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1237. [7.599011] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1238. [7.605490] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1239. [7.613130] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1240. [7.620770] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1241. [7.629668] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1242. [7.637309] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1243. [7.645236] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1244.  
  1245. [7.653360] Link Status:
  1246. [7.655777] Lane0:
  1247. [7.657805] CR_Done : 0
  1248. [7.661190] Channel_EQ_Done: 0
  1249. [7.664573] Symbol_Locked : 0
  1250. [7.667957] Lane1:
  1251. [7.669988] CR_Done : 0
  1252. [7.673371] Channel_EQ_Done: 0
  1253. [7.676755] Symbol_Locked : 0
  1254. [7.680139] Interlane_Align_Done: 0
  1255. [7.683813] Adjust0:
  1256. [7.686036] Voltage_Swing: 1
  1257. [7.689228] Pre_Emph : 0
  1258. [7.692417] Adjust1:
  1259. [7.694639] Voltage_Swing: 1
  1260. [7.697829] Pre_Emph : 0
  1261.  
  1262. [7.701213] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1263. [7.707015] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1264. [7.714654] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1265. [7.721132] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1266. [7.728771] HW.GFX.GMA.Registers.Write: 0x84000013 -> 0x00064000:DDI_BUF_CTL_A
  1267. [7.736410] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1268. [7.744049] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1269. [7.751492] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1270. [7.757294] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1271. [7.764935] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1272. [7.772864] HW.GFX.GMA.Registers.Write: 0x01010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1273. [7.780794] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1274. [7.787274] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1275. [7.794913] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1276. [7.802551] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1277. [7.811450] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1278. [7.819089] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1279. [7.827117] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1280. [7.834221] HW.GFX.GMA.DP_Info.Read_Link_Status
  1281. [7.838863] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1282. [7.844665] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1283. [7.852304] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1284. [7.860236] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1285. [7.866716] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1286. [7.874356] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1287. [7.881995] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1288. [7.890893] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1289. [7.898529] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1290. [7.906457] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1291.  
  1292. [7.914581] Link Status:
  1293. [7.916997] Lane0:
  1294. [7.919028] CR_Done : 0
  1295. [7.922413] Channel_EQ_Done: 0
  1296. [7.925797] Symbol_Locked : 0
  1297. [7.929184] Lane1:
  1298. [7.931214] CR_Done : 0
  1299. [7.934600] Channel_EQ_Done: 0
  1300. [7.937985] Symbol_Locked : 0
  1301. [7.941371] Interlane_Align_Done: 0
  1302. [7.945045] Adjust0:
  1303. [7.947268] Voltage_Swing: 1
  1304. [7.950460] Pre_Emph : 0
  1305. [7.953651] Adjust1:
  1306. [7.955876] Voltage_Swing: 1
  1307. [7.959068] Pre_Emph : 0
  1308.  
  1309. [7.962453] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1310. [7.968257] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1311. [7.975898] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1312. [7.982377] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1313. [7.990017] HW.GFX.GMA.Registers.Write: 0x84000013 -> 0x00064000:DDI_BUF_CTL_A
  1314. [7.997656] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1315. [8.005293] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1316. [8.012741] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1317. [8.018543] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1318. [8.026184] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1319. [8.034114] HW.GFX.GMA.Registers.Write: 0x01010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1320. [8.042042] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1321. [8.048522] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1322. [8.056160] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1323. [8.063798] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1324. [8.072692] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1325. [8.080330] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1326. [8.088357] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1327. [8.095459] HW.GFX.GMA.DP_Info.Read_Link_Status
  1328. [8.100100] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1329. [8.105901] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1330. [8.113542] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1331. [8.121472] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1332. [8.127951] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1333. [8.135589] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1334. [8.143228] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1335. [8.152123] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1336. [8.159760] HW.GFX.GMA.Registers.Read: 0x00110080 <- 0x00064014:DDI_AUX_DATA_A_1
  1337. [8.167689] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1338.  
  1339. [8.175811] Link Status:
  1340. [8.178229] Lane0:
  1341. [8.180257] CR_Done : 1
  1342. [8.183641] Channel_EQ_Done: 0
  1343. [8.187025] Symbol_Locked : 0
  1344. [8.190409] Lane1:
  1345. [8.192438] CR_Done : 1
  1346. [8.195822] Channel_EQ_Done: 0
  1347. [8.199206] Symbol_Locked : 0
  1348. [8.202590] Interlane_Align_Done: 0
  1349. [8.206263] Adjust0:
  1350. [8.208486] Voltage_Swing: 1
  1351. [8.211677] Pre_Emph : 0
  1352. [8.214868] Adjust1:
  1353. [8.217091] Voltage_Swing: 1
  1354. [8.220282] Pre_Emph : 0
  1355.  
  1356. [8.223665] HW.GFX.GMA.Registers.Write: 0x80000180 -> 0x00064040:DP_TP_CTL_A
  1357. [8.231111] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1358. [8.238846] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1359. [8.244647] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1360. [8.252285] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1361. [8.260214] HW.GFX.GMA.Registers.Write: 0x22010100 -> 0x00064018:DDI_AUX_DATA_A_2
  1362. [8.268143] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1363. [8.274622] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1364. [8.282260] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1365. [8.289900] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1366. [8.298797] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1367. [8.306436] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1368. [8.314768] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1369. [8.321836] HW.GFX.GMA.DP_Info.Read_Link_Status
  1370. [8.326478] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1371. [8.332279] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1372. [8.339918] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1373. [8.347847] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1374. [8.354325] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1375. [8.361961] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1376. [8.369600] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1377. [8.378498] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1378. [8.386134] HW.GFX.GMA.Registers.Read: 0x00770081 <- 0x00064014:DDI_AUX_DATA_A_1
  1379. [8.394061] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1380.  
  1381. [8.402183] Link Status:
  1382. [8.404602] Lane0:
  1383. [8.406631] CR_Done : 1
  1384. [8.410015] Channel_EQ_Done: 1
  1385. [8.413398] Symbol_Locked : 1
  1386. [8.416783] Lane1:
  1387. [8.418812] CR_Done : 1
  1388. [8.422197] Channel_EQ_Done: 1
  1389. [8.425581] Symbol_Locked : 1
  1390. [8.428965] Interlane_Align_Done: 1
  1391. [8.432638] Adjust0:
  1392. [8.434862] Voltage_Swing: 1
  1393. [8.438052] Pre_Emph : 0
  1394. [8.441245] Adjust1:
  1395. [8.443468] Voltage_Swing: 1
  1396. [8.446661] Pre_Emph : 0
  1397.  
  1398. [8.450046] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1399. [8.457781] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1400. [8.463582] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1401. [8.471220] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064014:DDI_AUX_DATA_A_1
  1402. [8.479150] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1403. [8.487078] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1404. [8.493558] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1405. [8.501194] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  1406. [8.508832] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1407. [8.517729] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1408. [8.525364] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1409. [8.533292] HW.GFX.GMA.Registers.Write: 0x80000200 -> 0x00064040:DP_TP_CTL_A
  1410. [8.540739] HW.GFX.GMA.Registers.Write: 0x80000300 -> 0x00064040:DP_TP_CTL_A
  1411. [8.548183] HW.GFX.GMA.Pipe_Setup.On
  1412. [8.551760] HW.GFX.GMA.Transcoder.Setup
  1413. [8.555627] HW.GFX.GMA.Transcoder.Setup_Link
  1414. [8.559979] HW.GFX.GMA.DP_Info.Calculate_M_N
  1415. [8.564329] HW.GFX.GMA.Registers.Write: 0x7e627d27 -> 0x0006f030:PIPE_EDP_DATA_M1
  1416. [8.572257] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x0006f034:PIPE_EDP_DATA_N1
  1417. [8.580184] HW.GFX.GMA.Registers.Write: 0x00083518 -> 0x0006f040:PIPE_EDP_LINK_M1
  1418. [8.588111] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x0006f044:PIPE_EDP_LINK_N1
  1419. [8.596040] HW.GFX.GMA.Registers.Write: 0x00000021 -> 0x0006f410:PIPE_EDP_MSA_MISC
  1420. [8.604065] HW.GFX.GMA.Registers.Write: 0x081f077f -> 0x0006f000:HTOTAL_EDP
  1421. [8.611414] HW.GFX.GMA.Registers.Write: 0x081f077f -> 0x0006f004:HBLANK_EDP
  1422. [8.618760] HW.GFX.GMA.Registers.Write: 0x07cf07af -> 0x0006f008:HSYNC_EDP
  1423. [8.626013] HW.GFX.GMA.Registers.Write: 0x04560437 -> 0x0006f00c:VTOTAL_EDP
  1424. [8.633363] HW.GFX.GMA.Registers.Write: 0x04560437 -> 0x0006f010:VBLANK_EDP
  1425. [8.640713] HW.GFX.GMA.Registers.Write: 0x043f043a -> 0x0006f014:VSYNC_EDP
  1426. [8.647962] HW.GFX.GMA.Pipe_Setup.Setup_FB
  1427. [8.652120] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
  1428. [8.659371] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
  1429. [8.666622] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
  1430. [8.673970] HW.GFX.GMA.Pipe_Setup.Setup_Display
  1431. [8.678611] HW.GFX.GMA.Registers.Write: 0x009f0008 -> 0x0007027c:PLANE_BUF_CFG_1_A
  1432. [8.686636] HW.GFX.GMA.Registers.Write: 0x80008098 -> 0x00070240:PLANE_WM_1_A_0
  1433. [8.694371] HW.GFX.GMA.Registers.Write: 0x00070000 -> 0x0007017c:CUR_BUF_CFG_A
  1434. [8.702011] HW.GFX.GMA.Registers.Write: 0x80008008 -> 0x00070140:CUR_WM_A_0
  1435. [8.709359] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane
  1436. [8.714387] HW.GFX.GMA.Registers.Write: 0x84002000 -> 0x00070180:DSPACNTR
  1437. [8.721541] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF
  1438. [8.728988] HW.GFX.GMA.Registers.Write: 0x0437077f -> 0x00070190:PLANE_SIZE_1_A
  1439. [8.736724] HW.GFX.GMA.Registers.Write: 0x00000078 -> 0x00070188:DSPASTRIDE
  1440. [8.744074] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007018c:PLANE_POS_1_A
  1441. [8.751712] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF
  1442. [8.758871] HW.GFX.GMA.Registers.Write: 0x077f0437 -> 0x0006001c:PIPEASRC
  1443. [8.766026] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070030:PIPEAMISC
  1444. [8.773277] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A
  1445. [8.780143] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A
  1446. [8.787589] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A
  1447. [8.795036] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A
  1448. [8.802674] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A
  1449. [8.809538] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A
  1450. [8.816982] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A
  1451. [8.824428] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A
  1452. [8.832067] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
  1453. [8.839317] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
  1454. [8.846570] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
  1455. [8.853919] HW.GFX.GMA.Registers.Write: 0x82000002 -> 0x0006f400:PIPE_EDP_DDI_FUNC_CTL
  1456. [8.862332] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x0007f008:PIPE_EDP_CONF
  1457. [8.869970] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x0007f008:PIPE_EDP_CONF
  1458. [8.877608] HW.GFX.GMA.Connectors.Post_On
  1459. [8.881669] HW.GFX.GMA.Connectors.DDI.Post_On
  1460. [8.886115] HW.GFX.GMA.Panel.Backlight_On
  1461. [8.890177] HW.GFX.GMA.Registers.Set_Mask: 0x00000004 .S PCH_PP_CONTROL
  1462. [8.897147] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1463. [8.904872] HW.GFX.GMA.Registers.Write: 0x00000007 -> 0x000c7204:PCH_PP_CONTROL
  1464. [8.912617] Enabled port eDP
  1465. framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
  1466. x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
  1467. PCI: 00:02.0 init finished in 6828 msecs
  1468. PCI: 00:04.0 init
  1469. PCI: 00:04.0 init finished in 0 msecs
  1470. PCI: 00:14.0 init
  1471. PCI: 00:14.0 init finished in 0 msecs
  1472. PCI: 00:14.2 init
  1473. PCI: 00:14.2 init finished in 0 msecs
  1474. PCI: 00:15.0 init
  1475. I2C bus 0 version 0x3132312a
  1476. DW I2C bus 0 at 0x9122f000 (400 KHz)
  1477. PCI: 00:15.0 init finished in 6 msecs
  1478. PCI: 00:15.1 init
  1479. I2C bus 1 version 0x3132312a
  1480. DW I2C bus 1 at 0x91230000 (400 KHz)
  1481. PCI: 00:15.1 init finished in 6 msecs
  1482. PCI: 00:1c.0 init
  1483. Initializing PCH PCIe bridge.
  1484. PCI: 00:1c.0 init finished in 3 msecs
  1485. PCI: 00:1d.0 init
  1486. Initializing PCH PCIe bridge.
  1487. PCI: 00:1d.0 init finished in 3 msecs
  1488. PCI: 00:1f.0 init
  1489. IOAPIC: Initializing IOAPIC at 0xfec00000
  1490. IOAPIC: Bootstrap Processor Local APIC = 0x00
  1491. IOAPIC: ID = 0x02
  1492. PCI: 00:1f.0 init finished in 11 msecs
  1493. PCI: 00:1f.3 init
  1494. HDA: codec_mask = 01
  1495. HDA: Initializing codec #0
  1496. HDA: codec viddid: 10ec0269
  1497. HDA: verb not loaded
  1498. PCI: 00:1f.3 init finished in 15 msecs
  1499. PCI: 00:1f.4 init
  1500. PCI: 00:1f.4 init finished in 0 msecs
  1501. PCI: 01:00.0 init
  1502. PCI: 01:00.0 init finished in 0 msecs
  1503. PCI: 02:00.0 init
  1504. PCI: 02:00.0 init finished in 0 msecs
  1505. PNP: 004e.0 init
  1506. IT8987: Initializing keyboard.
  1507. PNP: 004e.0 init finished in 8 msecs
  1508. Devices initialized
  1509. BS: BS_DEV_INIT run times (exec / console): 6812 / 167 ms
  1510. FMAP: area SMMSTORE found @ 210000 (262144 bytes)
  1511. SF: Detected 00 0000 with sector size 0x1000, total 0x800000
  1512. smm store: 4 # blocks with size 0x10000
  1513. SMMSTORE: Setting up SMI handler
  1514. BS: BS_DEV_INIT exit times (exec / console): 0 / 18 ms
  1515. Finalize devices...
  1516. PCI: 00:17.0 final
  1517. Devices finalized
  1518. BS: BS_POST_DEVICE run times (exec / console): 0 / 6 ms
  1519. CBFS: Found 'fallback/dsdt.aml' @0x957c0 size 0x3e45 in mcache @0x7abfd1e8
  1520. CBFS: 'fallback/slic' not found.
  1521. ACPI: Writing ACPI tables at 7aa79000.
  1522. ACPI: * FACS
  1523. ACPI: * DSDT
  1524. PCI space above 4GB MMIO is at 0x27f000000, len = 0x7d81000000
  1525. ACPI: * FADT
  1526. SCI is IRQ9
  1527. ACPI: added table 1/32, length now 40
  1528. ACPI: * SSDT
  1529. Found 1 CPU(s) with 8 core(s) each.
  1530. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1531. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1532. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1533. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1534. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1535. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1536. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1537. PSS: 800MHz power 5920 control 0x800 status 0x800
  1538. PSS: 600MHz power 4335 control 0x600 status 0x600
  1539. PSS: 400MHz power 2820 control 0x400 status 0x400
  1540. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1541. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1542. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1543. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1544. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1545. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1546. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1547. PSS: 800MHz power 5920 control 0x800 status 0x800
  1548. PSS: 600MHz power 4335 control 0x600 status 0x600
  1549. PSS: 400MHz power 2820 control 0x400 status 0x400
  1550. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1551. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1552. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1553. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1554. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1555. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1556. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1557. PSS: 800MHz power 5920 control 0x800 status 0x800
  1558. PSS: 600MHz power 4335 control 0x600 status 0x600
  1559. PSS: 400MHz power 2820 control 0x400 status 0x400
  1560. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1561. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1562. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1563. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1564. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1565. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1566. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1567. PSS: 800MHz power 5920 control 0x800 status 0x800
  1568. PSS: 600MHz power 4335 control 0x600 status 0x600
  1569. PSS: 400MHz power 2820 control 0x400 status 0x400
  1570. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1571. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1572. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1573. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1574. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1575. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1576. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1577. PSS: 800MHz power 5920 control 0x800 status 0x800
  1578. PSS: 600MHz power 4335 control 0x600 status 0x600
  1579. PSS: 400MHz power 2820 control 0x400 status 0x400
  1580. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1581. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1582. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1583. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1584. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1585. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1586. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1587. PSS: 800MHz power 5920 control 0x800 status 0x800
  1588. PSS: 600MHz power 4335 control 0x600 status 0x600
  1589. PSS: 400MHz power 2820 control 0x400 status 0x400
  1590. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1591. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1592. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1593. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1594. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1595. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1596. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1597. PSS: 800MHz power 5920 control 0x800 status 0x800
  1598. PSS: 600MHz power 4335 control 0x600 status 0x600
  1599. PSS: 400MHz power 2820 control 0x400 status 0x400
  1600. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1601. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1602. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1603. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1604. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1605. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1606. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1607. PSS: 800MHz power 5920 control 0x800 status 0x800
  1608. PSS: 600MHz power 4335 control 0x600 status 0x600
  1609. PSS: 400MHz power 2820 control 0x400 status 0x400
  1610. \_SB.PCI0.I2C0.H02C: Touchpad at I2C: 00:2c
  1611. \_SB.PCI0.RP01.WF00: WIFI Device PCI: 01:00.0
  1612. ACPI: added table 2/32, length now 44
  1613. ACPI: * MCFG
  1614. ACPI: added table 3/32, length now 48
  1615. ACPI: * LPIT
  1616. ACPI: added table 4/32, length now 52
  1617. ACPI: * MADT
  1618. SCI is IRQ9
  1619. ACPI: added table 5/32, length now 56
  1620. current = 7aa7ed30
  1621. ACPI: * DMAR
  1622. ACPI: added table 6/32, length now 60
  1623. ACPI: added table 7/32, length now 64
  1624. ACPI: * HPET
  1625. ACPI: added table 8/32, length now 68
  1626. ACPI: done.
  1627. ACPI tables: 24176 bytes.
  1628. smbios_write_tables: 7aa78000
  1629. Create SMBIOS type 16
  1630. Create SMBIOS type 17
  1631. PCI: 01:00.0 (WIFI Device)
  1632. SMBIOS tables: 977 bytes.
  1633. Writing table forward entry at 0x00000500
  1634. Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum b534
  1635. Writing coreboot table at 0x7aa9d000
  1636. CBFS: Found 'cmos_layout.bin' @0xfce00 size 0x3ec in mcache @0x7abfd2ac
  1637. 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1638. 1. 0000000000001000-000000000009ffff: RAM
  1639. 2. 00000000000a0000-00000000000fffff: RESERVED
  1640. 3. 0000000000100000-000000007aa77fff: RAM
  1641. 4. 000000007aa78000-000000007aaf5fff: CONFIGURATION TABLES
  1642. 5. 000000007aaf6000-000000007abcffff: RAMSTAGE
  1643. 6. 000000007abd0000-000000007affffff: CONFIGURATION TABLES
  1644. 7. 000000007b000000-000000007fffffff: RESERVED
  1645. 8. 00000000e0000000-00000000efffffff: RESERVED
  1646. 9. 00000000fed10000-00000000fed19fff: RESERVED
  1647. 10. 00000000fed80000-00000000fed84fff: RESERVED
  1648. 11. 00000000fed90000-00000000fed91fff: RESERVED
  1649. 12. 0000000100000000-000000027effffff: RAM
  1650. Wrote coreboot table at: 0x7aa9d000, 0x8b4 bytes, checksum 604d
  1651. coreboot table: 2252 bytes.
  1652. IMD ROOT 0. 0x7afff000 0x00001000
  1653. IMD SMALL 1. 0x7affe000 0x00001000
  1654. FSP MEMORY 2. 0x7abfe000 0x00400000
  1655. RO MCACHE 3. 0x7abfd000 0x000003b8
  1656. CONSOLE 4. 0x7abdd000 0x00020000
  1657. TIME STAMP 5. 0x7abdc000 0x00000910
  1658. ROMSTG STCK 6. 0x7abdb000 0x00001000
  1659. AFTER CAR 7. 0x7abd0000 0x0000b000
  1660. RAMSTAGE 8. 0x7aaf5000 0x000db000
  1661. REFCODE 9. 0x7aac7000 0x0002e000
  1662. SMM BACKUP 10. 0x7aab7000 0x00010000
  1663. 4f444749 11. 0x7aab5000 0x00002000
  1664. 53534d32 12. 0x7aaa5000 0x00010000
  1665. COREBOOT 13. 0x7aa9d000 0x00008000
  1666. ACPI 14. 0x7aa79000 0x00024000
  1667. SMBIOS 15. 0x7aa78000 0x00000800
  1668. IMD small region:
  1669. IMD ROOT 0. 0x7affec00 0x00000400
  1670. FSP RUNTIME 1. 0x7affebe0 0x00000004
  1671. FMAP 2. 0x7affeaa0 0x00000134
  1672. POWER STATE 3. 0x7affea60 0x00000040
  1673. ROMSTAGE 4. 0x7affea40 0x00000004
  1674. MEM INFO 5. 0x7affe860 0x000001e0
  1675. ACPI GNVS 6. 0x7affe760 0x00000100
  1676. BS: BS_WRITE_TABLES run times (exec / console): 3 / 692 ms
  1677. MTRR: Physical address space:
  1678. 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
  1679. 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
  1680. 0x00000000000c0000 - 0x000000007b000000 size 0x7af40000 type 6
  1681. 0x000000007b000000 - 0x0000000080000000 size 0x05000000 type 0
  1682. 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
  1683. 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
  1684. 0x0000000100000000 - 0x000000027f000000 size 0x17f000000 type 6
  1685. MTRR: Fixed MSR 0x250 0x0606060606060606
  1686. MTRR: Fixed MSR 0x258 0x0606060606060606
  1687. MTRR: Fixed MSR 0x259 0x0000000000000000
  1688. MTRR: Fixed MSR 0x268 0x0606060606060606
  1689. MTRR: Fixed MSR 0x269 0x0606060606060606
  1690. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1691. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1692. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1693. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1694. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1695. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1696. CPU physical address size: 39 bits
  1697. MTRR: default type WB/UC MTRR counts: 6/6.
  1698. MTRR: UC selected as default type.
  1699. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
  1700. MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
  1701. MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
  1702. MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
  1703. MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
  1704. MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
  1705. MTRR: Fixed MSR 0x250 0x0606060606060606
  1706. MTRR: Fixed MSR 0x258 0x0606060606060606
  1707. MTRR: Fixed MSR 0x259 0x0000000000000000
  1708. MTRR: Fixed MSR 0x268 0x0606060606060606
  1709. MTRR: Fixed MSR 0x269 0x0606060606060606
  1710. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1711. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1712. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1713. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1714. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1715. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1716. MTRR: Fixed MSR 0x250 0x0606060606060606
  1717. CPU physical address size: 39 bits
  1718. MTRR: Fixed MSR 0x258 0x0606060606060606
  1719. MTRR: Fixed MSR 0x250 0x0606060606060606
  1720. MTRR: Fixed MSR 0x250 0x0606060606060606
  1721. MTRR: Fixed MSR 0x258 0x0606060606060606
  1722. MTRR: Fixed MSR 0x259 0x0000000000000000
  1723. MTRR: Fixed MSR 0x268 0x0606060606060606
  1724. MTRR: Fixed MSR 0x269 0x0606060606060606
  1725. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1726. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1727. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1728. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1729. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1730. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1731. MTRR: Fixed MSR 0x258 0x0606060606060606
  1732. CPU physical address size: 39 bits
  1733. MTRR: Fixed MSR 0x259 0x0000000000000000
  1734. MTRR: Fixed MSR 0x259 0x0000000000000000
  1735. MTRR: Fixed MSR 0x268 0x0606060606060606
  1736. MTRR: Fixed MSR 0x269 0x0606060606060606
  1737. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1738. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1739. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1740. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1741. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1742. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1743. MTRR: Fixed MSR 0x268 0x0606060606060606
  1744. MTRR: Fixed MSR 0x269 0x0606060606060606
  1745. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1746. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1747. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1748. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1749. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1750. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1751. MTRR: Fixed MSR 0x250 0x0606060606060606
  1752. MTRR: Fixed MSR 0x250 0x0606060606060606
  1753. MTRR: Fixed MSR 0x258 0x0606060606060606
  1754. MTRR: Fixed MSR 0x259 0x0000000000000000
  1755. MTRR: Fixed MSR 0x268 0x0606060606060606
  1756. MTRR: Fixed MSR 0x269 0x0606060606060606
  1757. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1758. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1759. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1760. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1761. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1762. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1763. MTRR: Fixed MSR 0x258 0x0606060606060606
  1764. CPU physical address size: 39 bits
  1765. MTRR: Fixed MSR 0x259 0x0000000000000000
  1766. CPU physical address size: 39 bits
  1767. CPU physical address size: 39 bits
  1768.  
  1769. MTRR check
  1770. Fixed MTRRs : Enabled
  1771. Variable MTRRs: Enabled
  1772.  
  1773. MTRR: Fixed MSR 0x250 0x0606060606060606
  1774. BS: BS_WRITE_TABLES exit times (exec / console): 255 / 146 ms
  1775. MTRR: Fixed MSR 0x258 0x0606060606060606
  1776. MTRR: Fixed MSR 0x259 0x0000000000000000
  1777. MTRR: Fixed MSR 0x268 0x0606060606060606
  1778. MTRR: Fixed MSR 0x269 0x0606060606060606
  1779. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1780. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1781. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1782. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1783. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1784. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1785. CBFS: Found 'fallback/payload' @0x126ec0 size 0xb8d7c in mcache @0x7abfd358
  1786. CPU physical address size: 39 bits
  1787. Checking segment from ROM address 0xffb970ec
  1788. MTRR: Fixed MSR 0x268 0x0606060606060606
  1789. Checking segment from ROM address 0xffb97108
  1790. MTRR: Fixed MSR 0x269 0x0606060606060606
  1791. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1792. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1793. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1794. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1795. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1796. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1797. Loading segment from ROM address 0xffb970ec
  1798. CPU physical address size: 39 bits
  1799. code (compression=1)
  1800. New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xffb97124 filesize 0xb8d44
  1801. Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000000b8d44
  1802. using LZMA
  1803. Loading segment from ROM address 0xffb97108
  1804. Entry Point 0x00803120
  1805. BS: BS_PAYLOAD_LOAD run times (exec / console): 402 / 48 ms
  1806. Finalizing chipset.
  1807. HECI: No CSE device
  1808. apm_control: Finalizing SMM.
  1809. APMC done.
  1810. BS: BS_PAYLOAD_LOAD exit times (exec / console): 5 / 8 ms
  1811. mp_park_aps done after 0 msecs.
  1812. Jumping to boot code at 0x00803120(0x7aa9d000)
  1813.  
  1814.  
Advertisement
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!