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Matqux

I2S_transmitter

Feb 27th, 2024
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 02/26/2024 09:38:28 AM
  7. // Design Name:
  8. // Module Name: I2S_transmitter
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22. //I2S transmitter: clk = bclk!
  23. module I2S_transmitter
  24. (
  25.     input wire clk,
  26.     input wire rstn,
  27.     output wire lrclk,
  28.     output wire bclk,
  29.     output wire sdo
  30. );
  31.  
  32. //Copy the input clk to clk
  33. assign bclk = clk;
  34.  
  35. //Generate rlclk
  36. reg [4:0] cntr;
  37. always @ (negedge clk)
  38. begin
  39.     if(rstn == 1'b0)
  40.         cntr <= 5'd0;
  41.     else
  42.         cntr <= cntr + 1;
  43. end
  44.  
  45. reg lrclk_reg;
  46. always @ (negedge clk)
  47. begin
  48.     if(rstn == 1'b0)
  49.         lrclk_reg <= 1'b0;
  50.     else if (cntr == 5'd31)
  51.         lrclk_reg <= ~lrclk_reg;
  52. end
  53. assign lrclk = lrclk_reg;
  54.  
  55. //Shift out data
  56. reg [31:0] ldata;
  57. reg [31:0] rdata;
  58. always @ (negedge clk)
  59. begin
  60.     if((rstn == 1'b0) || (cntr == 5'd31))
  61.     begin
  62.         ldata <= 32'h00fb5210;
  63.         rdata <= 32'h00279ade;
  64.     end
  65.     else if (lrclk_reg == 1'b1)
  66.         ldata <= {ldata[30:0], 1'b0};
  67.     else
  68.         rdata <= {rdata[30:0], 1'b0};
  69. end
  70. assign sdo = (lrclk_reg == 1'b1) ? ldata[31] : rdata[31];
  71.  
  72. endmodule
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