`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    14:34:52 09/23/2019
// Design Name:
// Module Name:    vsevenseg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vsevenseg(
    input [3:0] x,
    output [6:0] seg
    );
//7 segment display with logic expressions
//

// x format {msb, ., ., lsb}
// seg format {g, f, e, d, c, b, a}
// 3 expressions have been filled for students

  // segment a
   assign seg[0] = ~x[3]&x[2]&x[0]|x[2]&x[1]|~x[3]&x[1]|x[3]&~x[0]|x[3]&~x[2]&~x[1]|~x[2]&~x[0];
  // segment b
   assign seg[1] = ~x[3]&~x[2]|~x[2]&~x[0]|~x[3]&~x[1]&~x[0]|~x[3]&x[1]&x[0]|x[3]&~x[1]&x[0];
  // segment e
   assign seg[4] = x[3]&x[2]|x[3]&x[1]|~x[2]&~x[0]|x[1]&~x[0];


// students to fill in these 4 expressions
  // segment c
   assign seg[2] = ~x[3]&~x[1]|~x[3]&x[0]|~x[1]&x[0]|~x[3]&x[2]|x[3]&~x[2];

  // segment d
   assign seg[3] = ~x[3]&~x[2]&~x[0]|~x[2]&x[1]&x[0]|x[2]&~x[1]&x[0]|x[2]&x[1]&~x[0]|x[3]&~x[1]&~x[0];

  // segment f
  assign seg[5] = ~x[1]&~x[0]|x[2]&~x[0]|x[3]&~x[2]|x[3]&x[1]|~x[3]&x[2]&~x[1];

 // segment g
   assign seg[6] = ~x[2]&x[1]|x[1]&~x[0]|x[3]&~x[2]|x[3]&x[0]|~x[3]&x[2]&~x[1];

endmodule