`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   13:16:34 11/14/2018
// Design Name:   zad
// Module Name:   /home/stud2015/5stasiak/sem7/egzamin/egzamin/test.v
// Project Name:  egzamin
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: zad
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module test;

    // Inputs
    reg clk;
    reg rst;
    reg in;

    // Outputs
    wire ready;
    wire ovl;
    wire [clogb2(14)-1:0] data;

    // Instantiate the Unit Under Test (UUT)
    zad #(.range(14)) uut (
        .clk(clk),
        .rst(rst),
        .in(in),
        .ready(ready),
        .ovl(ovl),
        .data(data)
    );

    initial begin
        clk = 1'b0;
        forever #10 clk = ~clk;
    end

    initial begin
        rst = 1'b0;
        #5 rst = 1'b1;
        #10 rst = 1'b0;
    end

    always @(negedge clk)
        in <= {$random}%2;

    initial #5000 $finish;

// funkcja logarytmujaca
function integer clogb2(input integer value);
    begin
        value = value - 1;
        for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
            value = value >> 1;
    end
endfunction
endmodule