AccelCMDS

module AccelCMDs(
    input logic fpga_reset,
    input logic fpga_clk,
    input logic end_transaction,

    output logic [5:0] init_bit_count,
    output logic [5:0] data_bit_count,
    (* keep = "true", mark_debug = "true" *) output logic [47:0] cmd_to_accel,
    output logic start_transaction,
    output logic init_instruct,     // Flag to determine if instruction command
    output logic data_read          // Flag to determine if data read command
    );

    typedef enum logic [2:0] {
        IDLE,
        INIT_STEP_ONE,
        INIT_STEP_TWO,
        INIT_STEP_THREE,
        DATA,
        WAIT
    } e_state;

    e_state state;

    logic step_one_flag, step_two_flag, step_three_flag;

    localparam logic [7:0] ADDR1 = 8'h00;
    localparam logic [7:0] INIT_DATA1 = 8'b00000000;

    localparam logic [7:0] ADDR2 = 8'h2C;
    localparam logic [7:0] INIT_DATA2 = 8'b00000100;

    localparam logic [7:0] ADDR3 = 8'h2D;
    localparam logic [7:0] INIT_DATA3 = 8'b00000010;

    localparam logic [7:0] WRITE = 8'h0A;
    localparam logic [7:0] READ = 8'h0B;

    localparam logic [7:0] XDATA_L = 8'h0E;


    always_ff @(posedge fpga_clk) begin
        if (fpga_reset) begin
            init_bit_count <= 0;
            data_bit_count <= 0;
            cmd_to_accel <= 0;
            start_transaction <= 0;
            data_read <= 0;
            init_instruct <= 0;
            step_one_flag <= 0;
            step_two_flag <= 0;
            step_three_flag <= 0;
            state <= IDLE;
        end else begin
            start_transaction <= 0;

            case (state)
                IDLE: begin
                    if (end_transaction == 1) begin
                        state <= IDLE;
                    end else begin
                        if (step_one_flag == 0) begin
                            state             <= INIT_STEP_ONE;
                            init_bit_count    <= 24;
                        end else if (step_two_flag == 0) begin
                            state             <= INIT_STEP_TWO;
                            init_bit_count    <= 24;
                        end else if (step_three_flag == 0) begin
                            state             <= INIT_STEP_THREE;
                            init_bit_count    <= 24;
                        end else begin
                            state             <= DATA;
                            data_bit_count    <= 48;
                            init_bit_count    <= 16; // change from 16 to 24
                        end
                    end
                end

                INIT_STEP_ONE: begin
                        init_instruct     <= 1;
                        cmd_to_accel      <= {24'b0, READ, ADDR1, INIT_DATA1};
                        start_transaction <= 1;
                        step_one_flag     <= 1;
                        state             <= WAIT;
                end

                INIT_STEP_TWO: begin
                        init_instruct     <= 1;
                        cmd_to_accel      <= {24'b0, WRITE, ADDR2, INIT_DATA2};
                        start_transaction <= 1;
                        step_two_flag     <= 1;
                        state             <= WAIT;
                end

                INIT_STEP_THREE: begin
                        init_instruct     <= 1;
                        cmd_to_accel      <= {24'b0, WRITE, ADDR3, INIT_DATA3};
                        start_transaction <= 1;
                        step_three_flag   <= 1;
                        state             <= WAIT;
                end

                DATA: begin
                        init_instruct     <= 1;
                        data_read         <= 1;
                        start_transaction <= 1;
                        cmd_to_accel      <= {32'b0, READ, ADDR1};      //This is what is in the waveform SS, test to see if ACCEL can send back device ID.

                       // cmd_to_accel      <= {32'b0, READ, XDATA_L};
                        state             <= WAIT;
                end

                WAIT: begin
                    if (end_transaction == 1)
                        state <= IDLE;
                end
            endcase
        end
    end

endmodule