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  1.  
  2. def : Pat<(i32 (sub GPR32:$src1, (add GPR32:$src2, (mul GPR32:$src2, (i32 0))))),
  3. (InstTwoOperands GPR32:$src2, GPR32:$src1)>;
  4.  
  5.  
  6. constexpr static int64_t MatchTable0[] = {
  7. GIM_SwitchOpcode, /*MI*/0, /*[*/47, 133, /*)*//*default:*//*Label 2*/ 462,
  8. /*TargetOpcode::G_SUB*//*Label 0*/ 91, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  9. /*TargetOpcode::G_SELECT*//*Label 1*/ 245,
  10. // Label 0: @91
  11. GIM_Try, /*On fail goto*//*Label 3*/ 244,
  12. GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
  13. GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
  14. GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
  15. GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
  16. GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
  17. GIM_Try, /*On fail goto*//*Label 4*/ 178, // Rule ID 4 //
  18. GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
  19. GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
  20. GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
  21. GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
  22. GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_MUL,
  23. GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
  24. GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
  25. GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
  26. GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0,
  27. // MIs[1] src2
  28. GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
  29. GIM_CheckIsSafeToFold, /*InsnID*/1,
  30. GIM_CheckIsSafeToFold, /*InsnID*/2,
  31. // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, (add:{ *:[i32] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src2, 0:{ *:[i32] }), GPR32:{ *:[i32] }:$src2)) => (InstTwoOperands:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1)
  32. GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::InstTwoOperands,
  33. GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
  34. GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
  35. GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
  36. GIR_EraseFromParent, /*InsnID*/0,
  37. GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
  38. // GIR_Coverage, 4,
  39. GIR_Done,
  40. // Label 4: @178
  41. GIM_Try, /*On fail goto*//*Label 5*/ 243, // Rule ID 3 //
  42. GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
  43. GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
  44. GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
  45. GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
  46. GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
  47. GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
  48. GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_MUL,
  49. GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
  50. // MIs[2] src2
  51. GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
  52. GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0,
  53. GIM_CheckIsSafeToFold, /*InsnID*/1,
  54. GIM_CheckIsSafeToFold, /*InsnID*/2,
  55. // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src2, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src2, 0:{ *:[i32] }))) => (InstTwoOperands:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1)
  56. GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::InstTwoOperands,
  57. GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
  58. GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
  59. GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
  60. GIR_EraseFromParent, /*InsnID*/0,
  61. GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
  62. // GIR_Coverage, 3,
  63. GIR_Done,
  64. // Label 5: @243
  65. GIM_Reject,
  66. // Label 3: @244
  67. GIM_Reject,
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