Inlined thread locals

uint64_t getRandomUnsigned64() {
  static thread_local uint64_t RandomStateA =
      static_cast<uint64_t>(time(nullptr));
  static thread_local uint64_t RandomStateB = xorShiftStar64();

  uint64_t A = RandomStateA;
  const uint64_t B = RandomStateB;
  RandomStateA = B;

  A ^= A << 23;
  A ^= A >> 17;
  A ^= B ^ (B >> 26);

  RandomStateB = A;
  return A + B;
}

==========================================================================
00000000004006b0 <gwp_asan::random::getRandomUnsigned64()>:
  4006b0:       53                      push   %rbx
  4006b1:       66 66 66 64 48 8b 04    data16 data16 data16 mov %fs:0x0,%rax
  4006b8:       25 00 00 00 00
  4006bd:       48 89 c3                mov    %rax,%rbx
# TLS init check/branch for RandomStateA.
  4006c0:       80 b8 d8 ff ff ff 00    cmpb   $0x0,-0x28(%rax)
  4006c7:       74 51                   je     40071a <gwp_asan::random::getRandomUnsigned64()+0x6a> #
# TLS init check/branch for RandomStateB (with an unneccessary `%rbx = %rax` copy).
  4006c9:       48 89 d8                mov    %rbx,%rax
  4006cc:       80 bb e8 ff ff ff 01    cmpb   $0x1,-0x18(%rbx)
  4006d3:       75 6c                   jne    400741 <gwp_asan::random::getRandomUnsigned64()+0x91>
  4006d5:       48 89 d8                mov    %rbx,%rax
  4006d8:       48 8b 93 e0 ff ff ff    mov    -0x20(%rbx),%rdx
  4006df:       48 8b b3 d0 ff ff ff    mov    -0x30(%rbx),%rsi
  4006e6:       48 89 93 d0 ff ff ff    mov    %rdx,-0x30(%rbx)
  4006ed:       48 89 f1                mov    %rsi,%rcx
  4006f0:       48 c1 e1 17             shl    $0x17,%rcx
  4006f4:       48 31 f1                xor    %rsi,%rcx
  4006f7:       48 89 d0                mov    %rdx,%rax
  4006fa:       48 c1 e8 1a             shr    $0x1a,%rax
  4006fe:       48 31 d0                xor    %rdx,%rax
  400701:       48 31 c8                xor    %rcx,%rax
  400704:       48 c1 e9 11             shr    $0x11,%rcx
  400708:       48 31 c1                xor    %rax,%rcx
  40070b:       48 89 8b e0 ff ff ff    mov    %rcx,-0x20(%rbx)
  400712:       48 01 d1                add    %rdx,%rcx
  400715:       48 89 c8                mov    %rcx,%rax
  400718:       5b                      pop    %rbx
  400719:       c3                      retq