/*
Farshad Chowdhury
Verification of Digital Systems
Testbench for SRT

Purpose: This test bench was written to verify each transactor of the synchronous reciver transmitter.
This test bench was designed to test and verify the given code for the SRT to the given spec. This test stimulates the code
and ensures the code behaves in matter that correspeonds to the given software spec. This will ensure that there are no bugs
or unexpected behavoir.

*/

`timescale 1ns/1ns


module testbench;
integer i; //clock int
   reg       srt_clk_in;     // Clock Input
   reg      srt_rst_l_in;   // Active Low Reset Input
   // Bus Interface
   reg       srt_en_l_in;    // Active Low Bus Enable Input
   reg       srt_wr_l_in;    // Active Low Bus Enable Input
   reg       srt_rd_l_in;    // Active Low Bus Enable Input
   reg [4:0] srt_addr_in;    // Address Input
   reg [7:0] srt_data_inout; // Bidirectional Data Bus
   // Serial Interface
   reg       srt_ser_in;     // Serial Data Input
   reg      srt_ser_out;     // Serial Data Output

  //initialize DUT (SRT)

    srt UUT(
        .srt_clk_in(srt_clk_in),
        .srt_rst_l_in(srt_rst_l_in),
        .srt_en_l_in(srt_en_l_in),
        .srt_wr_l_in(srt_wr_l_in),
        .srt_rd_l_in(srt_rd_l_in),
        .srt_addr_in(srt_addr_in),
        .srt_data_inout(srt_data_inout),
        .srt_ser_in(srt_ser_in),
        .srt_ser_out(srt_ser_out)
    );
    initial begin
    $monitor(
        srt_clk_in,
        srt_rst_l_in,
        srt_en_l_in,
        srt_wr_l_in,
        srt_rd_l_in,
        srt_addr_in,
        srt_data_inout,
        srt_ser_in,
        srt_ser_out
    );
    for( i=0; i<1;i=(i+1)) begin
    srt_clk_in=i;
    end
end


endmodule // srt_tb