TheLegace

module Lab3(
                input CLOCK_50,
                input [3:0] KEY,
                output reg [7:0] HEX0,      //7-seg display 0
                output reg [7:0] HEX1,      //7-seg display 0
                output reg [7:0] HEX2,      //7-seg display 0
                output reg [7:0] HEX3,      //7-seg display 0
                output reg [17:0] LEDR
);

    reg [15:0] count;               //8-bit counter
    reg [15:0] push2,push1;             //count when pushbutton 3/KEY[2] is pushed
    reg flag;                       //set once pushbutton3/KEY[2] is pushed
    reg [15:0] elapsed;             //elapsed time between pushbutton3/KEY[2] and pushbutton2/KEY[1]
    wire [7:0] h0,h1,h2,h3;

    hex_7seg s0(push2[3:0], h0);
    hex_7seg s1(push2[7:4], h1);
    hex_7seg s2(push2[11:8], h2);
    hex_7seg s3(push2[15:12], h3);

    initial begin
        flag = 0;
        push1 = 0;
        push2 = 0;
        HEX0 = 7'b1000000;
        HEX1 = 7'b1000000;
        HEX2 = 7'b1000000;
        HEX3 = 7'b1000000;
    end

    always @ (posedge CLOCK_50)
        begin
            count <= count + 1;
            LEDR[0] = 0;
            LEDR[1] = 0;
            LEDR[2] = 0;
            HEX0 <= h0;
            HEX1 <= h1;
            HEX2 <= h2;
            HEX3 <= h3;
            //flag = 0;
            if(count >= 'b1100001101010000) begin
                elapsed <= elapsed + 1;
                count <= 0;
            end

            if(!KEY[0]) begin
                LEDR[0] = 1;
                flag = 1;
                push1 <= elapsed;
            end
            if(flag && !KEY[1]) begin
                LEDR[1] = 1;
                push2 <= elapsed - push1;
            end
            if(!flag && !KEY[1]) begin
                HEX0 <= 7'b0101111;
                HEX1 <= 7'b0100011;
                HEX2 <= 7'b0101111;
                HEX3 <= 7'b0000110;
                LEDR[2] = 1;
            end
        end

endmodule


module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
        4'h0: seg = 7'b1000000;
        4'h1: seg = 7'b1111001;     // ---a----
        4'h2: seg = 7'b0100100;     // |      |
        4'h3: seg = 7'b0110000;     // f      b
        4'h4: seg = 7'b0011001;     // |      |
        4'h5: seg = 7'b0010010;     // ---g----
        4'h6: seg = 7'b0000010;     // |      |
        4'h7: seg = 7'b1111000;     // e      c
        4'h8: seg = 7'b0000000;     // |      |
        4'h9: seg = 7'b0011000;     // ---d----
        4'ha: seg = 7'b0001000;
        4'hb: seg = 7'b0000011;
        4'hc: seg = 7'b1000110;
        4'hd: seg = 7'b0100001;
        4'he: seg = 7'b0000110;
        4'hf: seg = 7'b0001110;
endcase
endmodule


module dec_seg7(
                        input [3:0] dec,
                        input carryin,
                        output reg carryout,
                        seg
);
    integer d;
    always @ (dec)
    begin
        d = dec;
        if(carryin) begin
            d = d+1;
        end
        if(dec > 9) begin
            d = d-10;
            carryout = 1;
        end
        case (dec)
        4'h0: seg = 7'b1000000;
        4'h1: seg = 7'b1111001;     // ---a----
        4'h2: seg = 7'b0100100;     // |      |
        4'h3: seg = 7'b0110000;     // f      b
        4'h4: seg = 7'b0011001;     // |      |
        4'h5: seg = 7'b0010010;     // ---g----
        4'h6: seg = 7'b0000010;     // |      |
        4'h7: seg = 7'b1111000;     // e      c
        4'h8: seg = 7'b0000000;     // |      |
        4'h9: seg = 7'b0011000;     // ---d----
    endcase

    end
endmodule