module zad2(
    input [0:0] KEY,
    input [0:1] SW,
    output [0:6] HEX0, HEX1, HEX2, HEX3);

    wire [15:0] Q;
    counter_16_bits ex0(KEY[0],SW[0],SW[1],Q);

    decoder_hex_16 ex1(Q[15:12],HEX3);
    decoder_hex_16 ex2(Q[11:7],HEX2);
    decoder_hex_16 ex3(Q[7:4],HEX1);
    decoder_hex_16 ex4(Q[3:0],HEX0);

endmodule

module counter_16_bits
    #(parameter N=16)
    (input clk, aclr, enable,
    output reg [N-1:0] Q);

    always@(posedge clk, negedge aclr)
        if(!aclr) Q<={N{1'b0}};
        else if(enable) Q<=Q+1'b01;
        else Q<=Q;

endmodule