LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.ITCE211Project_library.ALL;

ENTITY MEengine IS

    PORT (
        eni, reset, clk : IN STD_LOGIC;
        mv : OUT STD_LOGIC_VECTOR (data_output - 1 DOWNTO 0)
    );
END MEengine;

ARCHITECTURE Behavioral OF MEengine IS
    COMPONENT pe IS
        PORT (
            numberin : INOUT STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
            numberout, number : INOUT STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
            clk, eni, reset : IN STD_LOGIC
        );

    END COMPONENT;


     ----------------------Signals-------------------------------------
    SIGNAL numberin : vector_array(data_width - 1 DOWNTO 0);
    SIGNAL numberout : vector_array (data_width - 1 DOWNTO 0);
    SIGNAL number : vector_array (data_width - 1 DOWNTO 0);

BEGIN
    ----------------------Generate  component-------------------------------------
    gen_pro_ele : FOR i IN 0 TO number_of_PE - 1 GENERATE
        Processing_Element : pe PORT MAP(
            numberin => numberin(i),
            numberout => numberout(i),
            number => number(i),
            clk => clk,
            reset => reset,
            eni => eni);
    END GENERATE gen_pro_ele;
END behavioral;