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  17. not-m153a/lab3/clk_div_2.v
  18. @yoshio99 yoshio99 new clock divider
  19. 9cbe7b8 1 minute ago
  20. 92 lines (79 sloc) 1.8 KB
  21.  
  22. `timescale 1ns / 1ps
  23. //////////////////////////////////////////////////////////////////////////////////
  24. // Company:
  25. // Engineer:
  26. //
  27. // Create Date: 21:04:30 02/24/2020
  28. // Design Name:
  29. // Module Name: clk_div_2
  30. // Project Name:
  31. // Target Devices:
  32. // Tool versions:
  33. // Description:
  34. //
  35. // Dependencies:
  36. //
  37. // Revision:
  38. // Revision 0.01 - File Created
  39. // Additional Comments:
  40. //
  41. //////////////////////////////////////////////////////////////////////////////////
  42. module clk_div_2(CLK, FAST_CLK, FOUR_CLK, ONETWENTY_CLK, BLINK_CLK, ONE_CLK
  43. );
  44.  
  45. input CLK;
  46. output reg FOUR_CLK;
  47. output reg ONETWENTY_CLK;
  48. output reg ONE_CLK;
  49. output reg BLINK_CLK;
  50. output reg FAST_CLK;
  51.  
  52. parameter constant1 = 12500000;
  53. parameter constant2 = 416666;
  54. parameter constant3 = 50000000;
  55. parameter constant4 = 25000000;
  56.  
  57.  
  58. reg [31:0] count1;
  59. reg [31:0] count2;
  60. reg [31:0] count3;
  61. reg [31:0] count4;
  62.  
  63. always @ (posedge CLK)
  64. begin
  65. if (count1 == constant1 - 1)
  66. count1 <= 32'b0;
  67. else
  68. count1 <= count1 + 1;
  69.  
  70. if (count2 == constant2 - 1)
  71. count2 <= 32'b0;
  72. else
  73. count2 <= count2 + 1;
  74.  
  75. if (count3 == constant3 - 1)
  76. count3 <= 32'b0;
  77. else
  78. count3 <= count3 + 1;
  79.  
  80. if (count4 == constant4 - 1)
  81. count4 <= 32'b0;
  82. else
  83. count4 <= count4 + 1;
  84. end
  85.  
  86. always @ (posedge CLK)
  87. begin
  88. if (count1 == constant1 - 1)
  89. FOUR_CLK <= ~FOUR_CLK;
  90. else
  91. FOUR_CLK <= FOUR_CLK;
  92.  
  93. if (count2 == constant2 - 1)
  94. ONETWENTY_CLK <= ~ONETWENTY_CLK;
  95. else
  96. ONETWENTY_CLK <= ONETWENTY_CLK;
  97.  
  98. if (count2 == constant2 - 1)
  99. FAST_CLK <= ~FAST_CLK;
  100. else
  101. FAST_CLK <= FAST_CLK;
  102.  
  103. if (count3 == constant3 - 1)
  104. ONE_CLK <= ~ONE_CLK;
  105. else
  106. ONE_CLK <= ONE_CLK;
  107.  
  108. if (count4 == constant4 - 1)
  109. BLINK_CLK <= ~BLINK_CLK;
  110. else
  111. BLINK_CLK <= BLINK_CLK;
  112. end
  113. endmodule
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