library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity comp is
port ( clk50: in std_logic;
		d1,d2: buffer std_logic_vector(6 downto 0);
		s: out std_logic_vector(7 downto 0)
		);
		end comp;
architecture arch of comp is
signal comp: std_logic_vector(23 downto 0);
signal clk1: std_logic;
signal u,d: std_logic_vector(3 downto 0);
begin
    process(clk50)
begin
	if(rising_edge(clk50))
		then comp<= comp+1;
		if(comp="10111110101111000010000000")
		then --clk1<=not clk1;
		comp<="00000000000000000000000000";
		end if;
	end if;
	end process;
clk1<=comp(23);
process(clk1)

begin
		if(rising_edge(clk1))
		then
			if(u="1001" and d="1001") then
			u<="0000";
			d<="0000";
		else u<=u+1;
		if(u="1001")then
			d<=d+1;
			u<="0000";
		end if;
			end if;
		end if;
end process;

process(u)
begin
case u is
            when"0000"=>s<= not"10111111";
            when"0001"=>s<= not"10000110";
            when"0010"=>s<= not"11011011";
            when"0011"=>s<= not"11001111";
            when"0100"=>s<= not"11100110";
            when"0101"=>s<= not"11101101";
            when"0110"=>s<= not"11111101";
            when"0111"=>s<= not"10000111";
            when"1000"=>s<= not"11111111";
            when"1001"=>s<= not"11101111";
            when others => null;
 end case;
 end process;

 process(d)
begin
case d is
            when"0000"=>s<= not"10111111";
            when"0001"=>s<= not"10000110";
            when"0010"=>s<= not"11011011";
            when"0011"=>s<= not"11001111";
            when"0100"=>s<= not"11100110";
            when"0101"=>s<= not"11101101";
            when"0110"=>s<= not"11111101";
            when"0111"=>s<= not"10000111";
            when"1000"=>s<= not"11111111";
            when"1001"=>s<= not"11101111";
            when others => null;
 end case;
 end process;



end arch;