timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/26/2020 10:11:07 PM
// Design Name:
// Module Name: HazardUnit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module HazardUnit
(
input [4:0] RsD, RtD, RsE, RtE, RFAE, RFAM, RFAW,
output stall,
output reg flush,
output reg  ForwardAD, ForwardBD,
output reg [1:0] ForwardAE, ForwardBE,
input RFWEe, Branchd, MtoRFSele, RFWEm, RFWEw,  MtoRFSelm, Jump
    );
      reg LWstall, BStall;

    always @(*) begin
    ForwardAE <= 2'b00;
    ForwardBE <= 2'b00;
        //first 3 to 1 mux with ForwardAE
        if ((RsE != 0) && (RsE == RFAM) && (RFWEm)) begin
            ForwardAE <= 2'b10;
            end
         else if ((RsE != 0) && (RFWEw) && (RsE == RFAW)) begin
            ForwardAE <= 2'b01;
            end
         else begin
            ForwardAE <= 2'b00;
           end
         //second 3 to 1 mux with ForwardBE
         if ((RtE != 0) && (RtE == RFAM) && (RFWEm)) begin
            ForwardBE <= 2'b10;
            end
          else if ((RtE != 0) && (RFWEw) && (RtE == RFAW)) begin
            ForwardBE <= 2'b01;
            end
          else begin
            ForwardBE <= 2'b00;
            end
          //ForwardAD mux
          if ((RsD != 0) && (RsD == RFAM) && (RFWEm)) begin
            ForwardAD <= 1'b1;
            end
          else begin
            ForwardAD <= 1'b0;
            end
           //ForwardBD mux
           if ((RtD != 0) && (RtD == RFAM) && (RFWEm)) begin
                ForwardBD <= 1'b1;
            end
            else begin
                ForwardBD <= 1'b0;
            end
            //LW STALL
            if ((MtoRFSele && ((RtE == RsD) || (RtE == RtD)))) begin
                 LWstall <= 1'b1;
                flush <= 1'b1;
              end
            else begin
                LWstall <= 1'b0;
                flush <= 1'b0;
                end

             //Branch STall
             if (((RsD == RFAE) || (RtD == RFAE)) && (Branchd) && (RFWEe) || ((RsD == RFAM) || (RtD == RFAM)) && (Branchd) && (MtoRFSelm)) begin
                BStall <= 1'b1;
                end
              else begin
                BStall <= 1'b0;
                end

           //flush <= stall;
          end
          assign stall = LWstall | BStall;

endmodule