library ieee;
use ieee.std_logic_1164.all;

entity rom_mu1 is
port (
		addr: in std_logic_vector(3 downto 0);
		data: out std_logic_vector(3 downto 0)
		);
		end rom_mu1;

		architecture behavioural of rom_mu1 is

		type rom is array (0 to 15) of std_logic_vector( 3 downto 0 );

		constant mu1: rom:=(
										0 => x"0",
										1 => x"0",
										2 => x"0",
										3 => x"0",
										4 => x"0",
										5 => x"1",
										6 => x"2",
										7 => x"3",
										8 => x"0",
										9 => x"2",
										10 => x"4",
										11 => x"6",
										12 => x"0",
										13 => x"3",
										14 => x"6",
										15 => x"9"
										);

		begin

		process(addr)
		begin

		case addr is

		when "00" => data <= decoder(0);
		when "01" => data <= decoder(1);
		when "10" => data <= decoder(2);
		when others => data <= decoder(3);

		end case;
		end process;






		end behavioural;