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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Dept. of Computer Science, National Chiao Tung University
  4. // Engineer: Chun-Jen Tsai
  5. //
  6. // Create Date: 2017/05/08 15:29:41
  7. // Design Name:
  8. // Module Name: lab6
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description: The sample top module of lab 6: sd card reader. The behavior of
  13. //              this module is as follows
  14. //              1. When the SD card is initialized, display a message on the LCD.
  15. //                 If the initialization fails, an error message will be shown.
  16. //              2. The user can then press usr_btn[2] to trigger the sd card
  17. //                 controller to read the super block of the sd card (located at
  18. //                 block # 8192) into the SRAM memory.
  19. //              3. During SD card reading time, the four LED lights will be turned on.
  20. //                 They will be turned off when the reading is done.
  21. //              4. The LCD will then displayer the sector just been read, and the
  22. //                 first byte of the sector.
  23. //              5. Everytime you press usr_btn[2], the next byte will be displayed.
  24. //
  25. // Dependencies: clk_divider, LCD_module, debounce, sd_card
  26. //
  27. // Revision:
  28. // Revision 0.01 - File Created
  29. // Additional Comments:
  30. //
  31. //////////////////////////////////////////////////////////////////////////////////
  32.  
  33.  
  34.  
  35. module lab6(
  36.   // General system I/O ports
  37.   input  clk,
  38.   input  reset_n,
  39.   input  [3:0] usr_btn,
  40.   output [3:0] usr_led,
  41.  
  42.   // SD card specific I/O ports
  43.   output spi_ss,
  44.   output spi_sck,
  45.   output spi_mosi,
  46.   input  spi_miso,
  47.  
  48.   // 1602 LCD Module Interface
  49.   output LCD_RS,
  50.   output LCD_RW,
  51.   output LCD_E,
  52.   output [3:0] LCD_D
  53. );
  54.  
  55. localparam [2:0] S_MAIN_INIT = 3'b000, S_MAIN_IDLE = 3'b001,
  56.                  S_MAIN_WAIT = 3'b010, S_MAIN_READ = 3'b011,
  57.                  S_MAIN_DONE = 3'b100, S_MAIN_SHOW = 3'b101,
  58.                  S_MAIN_STOP = 3'b110;
  59. // Declare system variables
  60. wire btn_level, btn_pressed;
  61. reg  prev_btn_level;
  62. reg  [5:0] send_counter;
  63. reg  [2:0] P, P_next;
  64. reg  [9:0] sd_counter;
  65. reg  [7:0] data_byte;
  66. reg  [31:0] blk_addr;
  67.  
  68. reg  [127:0] row_A = "SD card cannot  ";
  69. reg  [127:0] row_B = "be initialized! ";
  70. reg  done_flag; // Signals the completion of reading one SD sector.
  71.  
  72. // Declare SD card interface signals
  73. wire clk_sel;
  74. wire clk_500k;
  75. reg  rd_req;
  76. reg  [31:0] rd_addr;
  77. wire init_finished;
  78. wire [7:0] sd_dout;
  79. wire sd_valid;
  80.  
  81. // Declare the control/data signals of an SRAM memory block
  82. wire [7:0] data_in;
  83. wire [7:0] data_out;
  84. wire [8:0] sram_addr;
  85. wire       sram_we, sram_en;
  86.  
  87. assign clk_sel = (init_finished)? clk : clk_500k; // clock for the SD controller
  88.  
  89. /*
  90. assign usr_led[3] = sram_we;
  91. assign usr_led[2] = (P == S_MAIN_READ);
  92. assign usr_led[1] = (P == S_MAIN_DONE);
  93. assign usr_led[0] = (P == S_MAIN_SHOW);
  94. */
  95.  
  96. clk_divider#(200) clk_divider0(
  97.   .clk(clk),
  98.   .reset(~reset_n),
  99.   .clk_out(clk_500k)
  100. );
  101.  
  102. debounce btn_db0(
  103.   .clk(clk),
  104.   .btn_input(usr_btn[2]),
  105.   .btn_output(btn_level)
  106. );
  107.  
  108. LCD_module lcd0(
  109.   .clk(clk),
  110.   .reset(~reset_n),
  111.   .row_A(row_A),
  112.   .row_B(row_B),
  113.   .LCD_E(LCD_E),
  114.   .LCD_RS(LCD_RS),
  115.   .LCD_RW(LCD_RW),
  116.   .LCD_D(LCD_D)
  117. );
  118.  
  119. sd_card sd_card0(
  120.   .cs(spi_ss),
  121.   .sclk(spi_sck),
  122.   .mosi(spi_mosi),
  123.   .miso(spi_miso),
  124.  
  125.   .clk(clk_sel),
  126.   .rst(~reset_n),
  127.   .rd_req(rd_req),
  128.   .block_addr(rd_addr),
  129.   .init_finished(init_finished),
  130.   .dout(sd_dout),
  131.   .sd_valid(sd_valid)
  132. );
  133.  
  134. sram ram0(
  135.   .clk(clk),
  136.   .we(sram_we),
  137.   .en(sram_en),
  138.   .addr(sram_addr),
  139.   .data_i(data_in),
  140.   .data_o(data_out)
  141. );
  142.  
  143. //
  144. // Enable one cycle of btn_pressed per each button hit
  145. //
  146. always @(posedge clk) begin
  147.   if (~reset_n)
  148.     prev_btn_level <= 0;
  149.   else
  150.     prev_btn_level <= btn_level;
  151. end
  152.  
  153. assign btn_pressed = (btn_level == 1 && prev_btn_level == 0)? 1 : 0;
  154.  
  155. // ------------------------------------------------------------------------
  156. // The following code sets the control signals of an SRAM memory block
  157. // that is connected to the data output port of the SD controller.
  158. // Once the read request is made to the SD controller, 512 bytes of data
  159. // will be sequentially read into the SRAM memory block, one byte per
  160. // clock cycle (as long as the sd_valid signal is high).
  161. assign sram_we = sd_valid;          // Write data into SRAM when sd_valid is high.
  162. assign sram_en = 1;                 // Always enable the SRAM block.
  163. assign data_in = sd_dout;           // Input data always comes from the SD controller.
  164. assign sram_addr = sd_counter[8:0]; // Set the driver of the SRAM address signal.
  165. // End of the SRAM memory block
  166. // ------------------------------------------------------------------------
  167. reg [63:0] scan_wd = 0;
  168. reg [31:0] tag_blk = 0;
  169.  
  170. always @(posedge clk) begin
  171.   if (~reset_n) begin
  172.     scan_wd <= 0;
  173.     tag_blk <= 0;
  174.   end
  175.   else if (P == S_MAIN_SHOW) begin
  176.     scan_wd = { scan_wd[55:0], data_byte };
  177.     if (scan_wd == "DLAB_TAG")
  178.       tag_blk <= blk_addr;
  179.     end
  180.     else begin
  181.       tag_blk <= tag_blk;
  182.     end
  183. end
  184.  
  185. // ------------------------------------------------------------------------
  186. // FSM of the SD card reader that reads the super block (512 bytes)
  187. always @(posedge clk) begin
  188.   if (~reset_n) begin
  189.     P <= S_MAIN_INIT;
  190.     done_flag <= 0;
  191.   end
  192.   else begin
  193.     P <= P_next;
  194.     if (P == S_MAIN_DONE)
  195.       done_flag <= 1;
  196.     else if (P == S_MAIN_SHOW && (P_next == S_MAIN_WAIT || P_next == S_MAIN_STOP))
  197.       done_flag <= 0;
  198.     else
  199.       done_flag <= done_flag;
  200.   end
  201. end
  202.  
  203. always @(*) begin // FSM next-state logic
  204.   case (P)
  205.     S_MAIN_INIT: // wait for SD card initialization
  206.       if (init_finished == 1) P_next = S_MAIN_IDLE;
  207.       else P_next = S_MAIN_INIT;
  208.     S_MAIN_IDLE: // wait for button click
  209.       if (btn_pressed == 1) P_next = S_MAIN_WAIT;
  210.       else P_next = S_MAIN_IDLE;
  211.     S_MAIN_WAIT: // issue a rd_req to the SD controller until it's ready
  212.       P_next = S_MAIN_READ;
  213.     S_MAIN_READ: // wait for the input data to enter the SRAM buffer
  214.       if (sd_counter == 512) P_next = S_MAIN_DONE;
  215.       else P_next = S_MAIN_READ;
  216.     S_MAIN_DONE: // read byte 0 of the superblock from sram[]
  217.       //P_next = S_MAIN_SHOW;
  218.       if (btn_pressed) P_next = S_MAIN_SHOW;
  219.       else P_next = S_MAIN_SHOW;
  220.     S_MAIN_SHOW:
  221.       if (sd_counter < 512) P_next = S_MAIN_DONE;
  222.       else if (blk_addr == 32'h4080) P_next = S_MAIN_STOP;
  223.         else P_next = S_MAIN_WAIT;
  224.     S_MAIN_STOP:
  225.       if (!btn_pressed) P_next = S_MAIN_STOP;
  226.       else P_next = S_MAIN_IDLE;
  227.     default:
  228.       P_next = S_MAIN_IDLE;
  229.   endcase
  230. end
  231.  
  232. // FSM output logic: controls the 'rd_req' and 'rd_addr' signals.
  233. always @(*) begin
  234.   rd_req = (P == S_MAIN_WAIT);
  235.   rd_addr = blk_addr;
  236. end
  237.  
  238. always @(posedge clk) begin
  239.   if (~reset_n) blk_addr <= 32'h4080;
  240.   else if (P == S_MAIN_SHOW && P_next == S_MAIN_WAIT)begin
  241.       blk_addr <= blk_addr + 1; // In lab 6, change this line to scan all blocks
  242.   end else blk_addr <= blk_addr;
  243. end
  244.  
  245. // FSM output logic: controls the 'sd_counter' signal.
  246. // SD card read address incrementer
  247. always @(posedge clk) begin
  248.   if (~reset_n ||
  249.       (P == S_MAIN_READ && P_next == S_MAIN_DONE) ||
  250.       (P == S_MAIN_WAIT)
  251.      )
  252.     sd_counter <= 0;
  253.   else if ((P == S_MAIN_READ && sd_valid) ||
  254.            (P == S_MAIN_DONE && P_next == S_MAIN_SHOW))
  255.     sd_counter <= sd_counter + 1;
  256. end
  257.  
  258. // FSM ouput logic: Retrieves the content of sram[] for display
  259. always @(posedge clk) begin
  260.   if (~reset_n) data_byte <= 8'b0;
  261.   else if (sram_en && P == S_MAIN_DONE) data_byte <= data_out;
  262. end
  263. // End of the FSM of the SD card reader
  264. // ------------------------------------------------------------------------
  265.  
  266. // ------------------------------------------------------------------------
  267. // LCD Display function.
  268. always @(posedge clk) begin
  269.   if (~reset_n) begin
  270.     row_A = "SD card cannot  ";
  271.     row_B = "be initialized! ";
  272.   end
  273.   else if (done_flag) begin
  274.     row_A <= { "block:    ",
  275.                 ((blk_addr[23:20] > 9)? "7" : "0") + blk_addr[23:20],
  276.                 ((blk_addr[19:16] > 9)? "7" : "0") + blk_addr[19:16],
  277.                 ((blk_addr[15:12] > 9)? "7" : "0") + blk_addr[15:12],
  278.                 ((blk_addr[11: 8] > 9)? "7" : "0") + blk_addr[11: 8],
  279.                 ((blk_addr[ 7: 4] > 9)? "7" : "0") + blk_addr[ 7: 4],
  280.                 ((blk_addr[ 3: 0] > 9)? "7" : "0") + blk_addr[ 3: 0]
  281.              };
  282.     row_B <= { "        ",
  283.                scan_wd[63:56],
  284.                scan_wd[55:48],
  285.                scan_wd[47:40],
  286.                scan_wd[39:32],
  287.                scan_wd[31:24],
  288.                scan_wd[23:16],
  289.                scan_wd[15: 8],
  290.                scan_wd[ 7: 0]
  291.              };
  292.   end
  293.   else if (P == S_MAIN_IDLE) begin
  294.     row_A <= "IDLE            ";
  295.       row_B <= { "          ",
  296.     ((blk_addr[23:20] > 9)? "7" : "0") + blk_addr[23:20],
  297.     ((blk_addr[19:16] > 9)? "7" : "0") + blk_addr[19:16],
  298.     ((blk_addr[15:12] > 9)? "7" : "0") + blk_addr[15:12],
  299.     ((blk_addr[11: 8] > 9)? "7" : "0") + blk_addr[11: 8],
  300.     ((blk_addr[7:4] > 9)? "7" : "0") + blk_addr[7:4],
  301.     ((blk_addr[3:0] > 9)? "7" : "0") + blk_addr[3:0]
  302.              };
  303.   end
  304.   else if (P == S_MAIN_STOP) begin
  305.     row_A <= { "tag_blk:  ",
  306.                 ((tag_blk[23:20] > 9)? "7" : "0") + tag_blk[23:20],
  307.                 ((tag_blk[19:16] > 9)? "7" : "0") + tag_blk[19:16],
  308.                 ((tag_blk[15:12] > 9)? "7" : "0") + tag_blk[15:12],
  309.                 ((tag_blk[11: 8] > 9)? "7" : "0") + tag_blk[11: 8],
  310.                 ((tag_blk[ 7: 4] > 9)? "7" : "0") + tag_blk[ 7: 4],
  311.                 ((tag_blk[ 3: 0] > 9)? "7" : "0") + tag_blk[ 3: 0]
  312.              };
  313.     row_B <= { "        ",
  314.                scan_wd[63:56],
  315.                scan_wd[55:48],
  316.                scan_wd[47:40],
  317.                scan_wd[39:32],
  318.                scan_wd[31:24],
  319.                scan_wd[23:16],
  320.                scan_wd[15: 8],
  321.                scan_wd[ 7: 0]
  322.              };
  323.   end
  324.   else begin
  325.     row_A <= "Scanning    ... ";
  326.     row_B <= "the SD card ... ";
  327.   end
  328. end
  329. // End of the LCD display function
  330. // ------------------------------------------------------------------------
  331.  
  332. endmodule
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