module dec_2s (
  input [1:0] s,
  input e,
  output reg[3:0] o
  );
  always @ (*) begin
    o=4'd0;
    if (e) o[s]=1'd1;
  end
endmodule

module rgst# (
  parameter w=8
  )(
  input clk,rst_b,ld,clr,
  input [w-1:0] d,
  output reg [w-1:0] q
  );

  always @ (posedge clk ,negedge rst_b)
   if (!rst_b) q<=1'd0;
   else if (clr) q<=1'd0;
   else if (ld) q<=d;

   endmodule
   module reg_f1 (
     input clk,rst_b,wr_e,
     input [1:0] wr_addr,
     input [6:0] wr_data,
     input [1:0] rd_addr,
     output [6:0] rd_data
     );
     wire [3:0] a;
     wire [6:0] q0,q1,q2,q3;

     dec_2s i1 (
     .s(wr_adr),
     .e(wr_e),
     .o(a)
     );
     rgst #(.w(7)) i2 (
     .clk(clk),
     .rst_b(rst_b),
     .clr(1'd0),
     .ld(a[0]),
     .d(wr_data),
     .q(q0)
     );

     mux_2s #(.w(7)) i6 (
     .s(rd_addr),
     .do(qo),
     .d1(q1),
     .d2(q2),
     .d3(q3),
     .o(rd_data)
     );

   endmodule
   /////////////////////////////////////////////


module mux_2s # (
  parameter w=8
  )(
  input[1:0] s,
  input[w-1:0] d0,d1,d2,d3,
  output reg [w-1:0] o
  );

  always @(*)
   if(s==2'd3) o=d3;
   else if (s== 2'd2) o=d2;
   else if (s==2'd1) o=d1;
   else o=d0;
endmodule
module mux_2s_tb (
output reg[1:0] s,d0,d1,d2,d3,
output [1:0] o
);

mux_2s #(.w(2)) cut (
.d0(d0) ,
.d1(d1) ,
.d2(d2) ,
.d3(d3) ,
.s(s),
.o(o)
);


integer i;
initial begin

  {s,d0,d1,d2,d3}=10'd0;
  for (i=1;i<1024;i=i+1)
  #100 {s,d0,d1,d2,d3} =i[9:0];

end
endmodule;