`define STATUS_REGISTER 5'd12
`define CAUSE_REGISTER  5'd13
`define EPC_REGISTER    5'd14

module cp0(rd_data, EPC, TakenInterrupt,
          wr_data, regnum, next_pc,
          MTC0, ERET, TimerInterrupt, clock, reset);
   output [31:0] rd_data;
   output [29:0] EPC;
   output        TakenInterrupt;
   input  [31:0] wr_data;
   input   [4:0] regnum;
   input  [29:0] next_pc;
   input         MTC0, ERET, TimerInterrupt, clock, reset;

   wire and1_out, not1_out, and2_out, and3_out, reset_or_out, or1_out, exception_level;
   wire [31:0] cause_register, user_status,decoder_out, ext_epc_out, status_register;
   wire [29:0] epcReg_out, epc_in;

   // your Verilog for coprocessor 0 goes here

register userStatusReg(user_status, wr_data, clock, decoder_out[12], reset);

assign reset_or_out = (ERET | reset);
dffe exceptionStatusReg(exception_level,1'b1,clock,and3_out,reset_or_out);
decoder32 mtcDecoder(decoder_out,regnum,MTC0);

mux2v #(30) pcOrWriteData(epc_in, wr_data[31:2], next_pc,and3_out);

assign ext_epc_out = {epcReg_out,2'b00};
mux3v #(32) finalData(rd_data,status_register,cause_register,ext_epc_out,regnum);

assign EPC = epcReg_out;

// module register(q, d, clk, enable, reset);
or or1(or1_out, decoder_out[14], and3_out);

register #(30) epcReg(epcReg_out, epc_in, clock, or1_out, reset);

and and1(and1_out, cause_register[15], user_status[15]);
not not1(not1_out, exception_level);
and and2(and2_out, not1_out, user_status[0]);
and and3(and3_out, and1_out, and2_out);

assign status_register[15:8] = user_status[15:8];
assign status_register[1] = exception_level;
assign status_register[0] = user_status[0];
assign status_register[7:2] = 6'b0;
assign status_register[31:16] = 16'b0;

assign cause_register[15] = TimerInterrupt;
assign cause_register[14:0] = 15'b0;
assign cause_register[31:16] = 16'b0;


// and3_out == TakenInterrupt
assign TakenInterrupt = and3_out;

endmodule