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-- Company:
-- Engineer:
--
-- Create Date: 03.12.2017 14:20:21
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( clk : in STD_LOGIC;
           btnU : in STD_LOGIC;
           btnD : in STD_LOGIC;
           an : out STD_LOGIC_VECTOR (3 downto 0);
           led : out STD_LOGIC_VECTOR (2 downto 0);
           seg : out STD_LOGIC_VECTOR (6 downto 0));
end top;

architecture Behavioral of top is

component up_down_select is
    Port ( clk : in  STD_LOGIC;
           up : in  STD_LOGIC;
           down : in  STD_LOGIC;
           clk_out : out  STD_LOGIC:='0';
           stan: out  STD_LOGIC_VECTOR (1 downto 0);
           dir : out  STD_LOGIC:='0');
end component;

component pwm2 is
    Port ( clk : in  STD_LOGIC;
           wyp : in  STD_LOGIC_VECTOR (3 downto 0);
           wyj : out std_logic);
end component;

component seg7_disp
Port ( clk : in STD_LOGIC;
           data : in STD_LOGIC_VECTOR (15 downto 0);
           an : out STD_LOGIC_VECTOR (3 downto 0);
           seg : out STD_LOGIC_VECTOR (6 downto 0));
end component;

component dzielnikc
  Generic (Fwy:integer:=10);
  Port ( clk : in  STD_LOGIC;
         clk_div : out  STD_LOGIC);
end component;


component licznik_rew
Port ( clk : in STD_LOGIC;
           kier : in STD_LOGIC;
           wyj : out STD_LOGIC_VECTOR (3 downto 0));
end component;

component debouncer
port (
		pb, clock_100hz 	: in	std_logic;
		pb_debounced		: out	std_logic
		);
end component;

signal clk_100Hz:STD_LOGIC:='0';
signal clk_1000Hz:STD_LOGIC:='0';
signal clk_licz:STD_LOGIC:='0';

signal pb_Up:STD_LOGIC:='0';
signal pb_Down:STD_LOGIC:='0';
signal kier:STD_LOGIC:='0';
signal licz:STD_LOGIC_VECTOR (3 downto 0):=(others=>'0');
signal data:STD_LOGIC_VECTOR (15 downto 0):=(others=>'0');





begin

data<="0000000000010000" when licz="1010" else "000000000000"&licz;

DZ1:dzielnikc
generic map (Fwy=>100)
port map(clk=>clk,clk_div=>clk_100Hz);

DZ2:dzielnikc
generic map (Fwy=>1000)
port map(clk=>clk,clk_div=>clk_1000Hz);

DB1:debouncer
port map(pb=>btnU,pb_debounced=>pb_Up,clock_100hz=>clk_100Hz);
DB2:debouncer
port map(pb=>btnD,pb_debounced=>pb_Down,clock_100hz=>clk_100Hz);

UDS1:up_down_select
Port map( clk =>clk_100Hz,up=>pb_Up,down=>pb_Down,clk_out=>clk_licz,stan=>led(1 downto 0), dir=>kier);

L1:licznik_rew
port map(clk=>clk_licz,kier=>kier,wyj=>licz);

Disp1:seg7_disp
port map(clk=>clk,data=>data,an=>an,seg=>seg);
PWM1:pwm2
port map ( clk=>clk_1000Hz,wyp=>licz,wyj=>led(2));

end Behavioral;