ex5_37

//ex5_37
module ex5_37_a(output reg y,output reg[2:0] state,input x,clk,reset);
    reg[2:0] next_state;
    parameter a=3'b000,b=3'b001,c=3'b010,d=3'b011,e=3'b100,f=3'b101,g=3'b110;
    always@(posedge clk,negedge reset)
        if(reset==0) state<=a;
        else state<=next_state;
    always @(state,x)
    begin
        y=0; //Default situation
        case  (state)
        a:if(x) begin next_state=b;y=0;end else begin next_state=a;y=0;end
        b:if(x) begin next_state=d;y=0;end else begin next_state=c;y=0;end
        c:if(x) begin next_state=d;y=0;end else begin next_state=a;y=0;end
        d:if(x) begin next_state=f;y=1;end else begin next_state=e;y=0;end
        e:if(x) begin next_state=f;y=1;end else begin next_state=a;y=0;end
        f:if(x) begin next_state=f;y=1;end else begin next_state=g;y=0;end
        g:if(x) begin next_state=f;y=1;end else begin next_state=a;y=0;end
        default:next_state=a; //self-correcting
        endcase
    end
endmodule

//ex5_37_b
module ex5_37_b(output reg y,output reg[2:0] state,input x,clk,reset);
    reg[2:0] next_state;
    parameter a=3'b000,b=3'b001,c=3'b010,d=3'b011,e=3'b100;
    always@(posedge clk,negedge reset)
        if(reset==0) state<=a;
        else state<=next_state;
    always @(state,x)
    begin
        y=0; //Default situation
        case  (state)
        a:if(x) begin next_state=b;y=0;end else begin next_state=a;y=0;end
        b:if(x) begin next_state=d;y=0;end else begin next_state=c;y=0;end
        c:if(x) begin next_state=d;y=0;end else begin next_state=a;y=0;end
        d:if(x) begin next_state=d;y=1;end else begin next_state=e;y=0;end
        e:if(x) begin next_state=d;y=1;end else begin next_state=a;y=0;end
        default:next_state=a; //self-correcting
        endcase
    end
endmodule

//Compare
module t_ex5_37();
    wire y_a,y_b;
    wire[2:0] state_a,state_b;
    reg x,clk,reset;

    ex5_37_a m0(y_a,state_a,x,clk,reset);
    ex5_37_b m1(y_b,state_b,x,clk,reset);

    initial begin clk=0; forever #5 clk =~ clk; end
    initial fork
        reset=1;
        x=0;
        #2 reset=0;
        #3 reset=1;
        #20 x=1;
        #40 x=0;
        #60 x=1;
        #100 x=0;
        #120 x=1;
        #160 x=0;
        #180 x=1;
        #200 $finish;
    join
endmodule