D-Type Flip Flop using task

/*------------------------------
D-Type Flip Flop
Positive edge trigger
Active LOW CLR and PR

Pin Assignment for Altera DE2 Dev Board
clk 27MHz
d   SW[0]
pr  SW[2]
clr SW[1]
q   LEDR[0]
------------------------------*/
module dflipfloptask (
    input clk, d,  pr, clr,
    output reg q );

always@(posedge clk)        // triggered on positive edge
    dff(clk, d, pr, clr, q);


task dff;
    input clock, data_in, preset, clear;
    output reg data_out;

    begin
        if(pr==0) q<= 1;    // active low preset
        else if(clr==0) q <= 0; // active low clr
        else q <= d;
    end
endtask

endmodule