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- DSD+ 2.39
- Adding NAC/RAN/DCC/RAS data to event log file entries
- Appending synthesized audio to file 'DSDPlus.wav'
- audio input device #1 = 'CABLE Output (VB-Audio Virtual '
- audio output device #1 = 'Altoparlanti (Dispositivo High '
- audio output device #2 = 'CABLE Input (VB-Audio Virtual C'
- audio output device #3 = 'Audio digitale (S/PDIF) (Dispos'
- audio output device #4 = 'Audio digitale (S/PDIF) (Dispos'
- audio input device #1 (CABLE Output (VB-Audio Virtual ) initialized
- audio output device #1 (Altoparlanti (Dispositivo High ) initialized
- Fusion decoding enabled
- D-STAR decoding enabled
- NXDN4800 decoding enabled
- NXDN9600 decoding enabled
- DMR/MotoTRBO decoding enabled
- P25 Phase 1 decoding enabled
- X2-TDMA decoding enabled
- ProVoice decoding enabled
- Sync:+DMR
- +DMR CACH ERR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0A 2B 5D 00 00 00 00 00 7E CA 39 58 .+].....~.9X
- Sync:+DMR
- +DMR CACH ERR slot1 BS DATA DCC=1 Idle ERR7
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=602 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 BA 72 00 00 40 11 7B 92 E..'.r..@.{.
- +DMR slot1 BS DATA DCC=1 CSBK [LB=1 CSBKO=56 (BS OB Act) FID=0 v16=0000 id1=16777215 id2=611]
- 38 00 0000 FFFFFF 000263
- 101110000000000000000000000000001111111111111111111111110000000000000010011000110010011010101010
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 5A 0D 00 29 68 0F A1 0F A1 ...Z..)h....
- Sync:+DMR
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data ERR13 01 13 5E 4A 17 1D 60 40 22 CB 94 05 ..^J..`@"...
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 42 20 B6 00 00 00 00 00 B2 88 DD 52 B .........R
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- +DMR CACH ERR slot1 BS DATA DCC=1 Idle ERR12
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR4
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR5
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=603 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 86 78 00 00 40 11 AF 8B E..'.x..@...
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 5B 0D 00 29 68 0F A1 0F A1 ...[..)h....
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data E0 25 F6 .%. LRRP; Tgt=10600 Src=603
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 42 25 D7 00 00 00 00 00 10 D1 AC 28 B%.........(
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR34
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=608 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 61 7D 00 00 40 11 D4 81 E..'a}..@...
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 60 0D 00 29 68 0F A1 0F A1 ...`..)h....
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 11 49 07 09 66 40 15 1A 33 04 [email protected].
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data E2 0C F3 ... LRRP; Tgt=10600 Src=608
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR27
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- Null SLCO
- +DMR CACH ERR slot1 BS DATA DCC=1 Idle ERR5
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle ERR1
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR12
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=612 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 B1 44 00 00 40 11 84 B6 E..'.D..@...
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 64 0D 00 29 68 0F A1 0F A1 ...d..)h....
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 86 2F 07 09 66 40 15 1E C1 04 .../..f@....
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data E2 1D F0 ... LRRP; Tgt=10600 Src=612
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=614 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 96 32 00 00 40 11 9F C6 E..'.2..@...
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 66 0D 00 29 68 0F A1 0F A1 ...f..)h....
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 A2 16 07 09 66 40 22 4E E4 05 ......f@"N..
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 42 04 44 B.D LRRP; Tgt=10600 Src=614
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- +DMR CACH ERR slot1 BS DATA DCC=1 Idle ERR2
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR5
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=611 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 65 72 00 00 40 11 D0 89 E..'er..@...
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 63 0D 00 29 68 0F A1 0F A1 ...c..)h....
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 25 49 07 09 66 40 15 16 1E 04 ..%I..f@....
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data E2 0D F4 ... LRRP; Tgt=10600 Src=611
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 CSBK Preamble 8004 Tgt=901 Src=10700
- CACH Sig ERR3
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=901 Src=10700 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=10 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 29 CC 0C 00 03 85 0F A8 0F A8 ..).........
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 0E 7A 72 29 C7 08 00 EE F7 ..zr).....
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- Raw data: 45 00 00 22 00 01 00 00 40 11 35 7A 0C 00 29 CC 0C 00 03 85 0F A8 0F A8 00 0E 7A 72 29 C7 08 00 EE F7 00 00 00 00 00 00 00 00 00 00 C0 9D 94 C2
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data ?; Tgt=901 Src=10700 Port=4008 4008
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR28
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- Null SLCO
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8014 Tgt=10500 Src=108
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8013 Tgt=10500 Src=108
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8012 Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8011 Tgt=10500 Src=108
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8010 Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800F Tgt=10500 Src=108
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800E Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800D Tgt=10500 Src=108
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800C Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800B Tgt=10500 Src=108
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800A Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8009 Tgt=10500 Src=108
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8008 Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8007 Tgt=10500 Src=108
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8006 Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8005 Tgt=10500 Src=108
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10500 Src=108 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=6 Last=0 Seq=0
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 45 01 00 26 9E 71 00 00 40 11 99 E5 E..&.q..@...
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 0C 00 00 6C 0D 00 29 04 0F A5 0F A5 ...l..).....
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 12 7A 7E 00 08 F0 20 03 31 30 38 ..z~... .108
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 00 .. ARS; Tgt=10500 Src=108
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR27
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8006 Tgt=108 Src=10500
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8005 Tgt=108 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8004 Tgt=108 Src=10500
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8003 Tgt=108 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=108 Src=10500 Conf=0 SAP=[4:IP Data] Blocks=3 Pad=0 Last=0 Seq=0
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 45 00 00 20 00 01 00 00 40 11 38 5D E.. [email protected]]
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 0D 00 29 04 0C 00 00 6C 0F A5 0F A5 ..)....l....
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 0C DF 18 00 02 BF 01 ........ ARS; Tgt=108 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot1 BS DATA DCC=1 Idle ERR27
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- Sync: no sync
- Sync:+DMR
- +DMR CACH ERR slot1 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble C003 Tgt=6000 Src=10600
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Data Header DPF=[2:UcData] TG=6000 Src=10600 Conf=0 SAP=[4:IP Data] Blocks=3 Pad=2 Last=0 Seq=0
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 45 00 00 1E 00 01 00 00 40 11 4B F6 [email protected].
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 0D 00 29 68 E1 00 17 70 0F A1 0F A1 ..)h...p....
- Activity update: Slot1=Group Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 0A AC BF 05 00 ...... LRRP; TG=6000 Src=10600
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- Activity update: Slot1=Group Data Slot2=No Activity
- +DMR slot1 BS DATA DCC=1 Idle ERR29
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- Sync: no sync
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=614 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 96 33 00 00 40 11 9F C5 E..'.3..@...
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 66 0D 00 29 68 0F A1 0F A1 ...f..)h....
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 7D 13 07 09 66 40 22 51 93 05 ..}...f@"Q..
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 42 04 BA B.. LRRP; Tgt=10600 Src=614
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data DE 57 4C 00 00 00 00 00 AC 83 B4 A5 .WL.........
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=604 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 8D 2C 00 00 40 11 A8 D6 E..'.,..@...
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 5C 0D 00 29 68 0F A1 0F A1 ...\..)h....
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 6A B5 07 09 66 40 22 98 2C 05 ..j...f@".,.
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 42 26 33 B&3 LRRP; Tgt=10600 Src=604
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR27
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8014 Tgt=10500 Src=124
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8013 Tgt=10500 Src=124
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8012 Tgt=10500 Src=124
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8011 Tgt=10500 Src=124
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8010 Tgt=10500 Src=124
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800F Tgt=10500 Src=124
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800E Tgt=10500 Src=124
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800D Tgt=10500 Src=124
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800C Tgt=10500 Src=124
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=611 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800B Tgt=10500 Src=124
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 65 73 00 00 40 11 D0 88 E..'es..@...
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800A Tgt=10500 Src=124
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 63 0D 00 29 68 0F A1 0F A1 ...c..)h....
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8009 Tgt=10500 Src=124
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 D7 48 07 09 66 40 15 16 A2 04 ...H..f@....
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8008 Tgt=10500 Src=124
- Activity update: Slot1=Indiv Data Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data E2 0D BE ... LRRP; Tgt=10600 Src=611
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8007 Tgt=10500 Src=124
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK ERR14 ECC FAIL
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8005 Tgt=10500 Src=124
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10500 Src=124 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=6 Last=0 Seq=0
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 45 01 00 26 95 2D 00 00 40 11 A3 19 E..&.-..@...
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 0C 00 00 7C 0D 00 29 04 0F A5 0F A5 ...|..).....
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 00 .. ARS; Tgt=10500 Src=124
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR27
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8006 Tgt=124 Src=10500
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8005 Tgt=124 Src=10500
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8004 Tgt=124 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8003 Tgt=124 Src=10500
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=612 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=124 Src=10500 Conf=0 SAP=[4:IP Data] Blocks=3 Pad=0 Last=0 Seq=0
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 B1 45 00 00 40 11 84 B5 E..'.E..@...
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 45 00 00 20 00 01 00 00 40 11 38 4D E.. [email protected]
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 64 0D 00 29 68 0F A1 0F A1 ...d..)h....
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 0D 00 29 04 0C 00 00 7C 0F A5 0F A5 ..)....|....
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 4C 2C 07 09 66 40 15 22 A9 04 ..L,..f@."..
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 0C DF 08 00 02 BF 01 ........ ARS; Tgt=124 Src=10500
- Activity update: Slot1=Indiv Data Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data E2 1D 42 ..B LRRP; Tgt=10600 Src=612
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR26
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync: no sync
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8014 Tgt=10500 Src=110
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8013 Tgt=10500 Src=110
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8012 Tgt=10500 Src=110
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8011 Tgt=10500 Src=110
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8010 Tgt=10500 Src=110
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800F Tgt=10500 Src=110
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800E Tgt=10500 Src=110
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800D Tgt=10500 Src=110
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800C Tgt=10500 Src=110
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800B Tgt=10500 Src=110
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 800A Tgt=10500 Src=110
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8009 Tgt=10500 Src=110
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8008 Tgt=10500 Src=110
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8007 Tgt=10500 Src=110
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8006 Tgt=10500 Src=110
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8005 Tgt=10500 Src=110
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10500 Src=110 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=6 Last=0 Seq=0
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 45 01 00 26 AB B0 00 00 40 11 8C A4 E..&....@...
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 0C 00 00 6E 0D 00 29 04 0F A5 0F A5 ...n..).....
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 12 79 64 00 08 F0 40 03 31 31 30 [email protected]
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 00 .. ARS; Tgt=10500 Src=110
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot1 BS DATA DCC=1 Idle ERR27
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8006 Tgt=110 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8005 Tgt=110 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8004 Tgt=110 Src=10500
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 CSBK Preamble 8003 Tgt=110 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=110 Src=10500 Conf=0 SAP=[4:IP Data] Blocks=3 Pad=0 Last=0 Seq=0
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 45 00 00 20 00 01 00 00 40 11 38 5B E.. [email protected][
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 0D 00 29 04 0C 00 00 6E 0F A5 0F A5 ..)....n....
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Rate 1/2 Data 00 0C DF 16 00 02 BF 01 ........ ARS; Tgt=110 Src=10500
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- Activity update: Slot1=Indiv Data Slot2=No Activity
- +DMR slot1 BS DATA DCC=1 Idle ERR28
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- Sync: no sync
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot2 BS DATA DCC=1 Data Header DPF=[2:UcData] Tgt=10600 Src=602 Conf=0 SAP=[4:IP Data] Blocks=4 Pad=5 Last=0 Seq=0
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 45 00 00 27 BA 73 00 00 40 11 7B 91 E..'.s..@.{.
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0C 00 02 5A 0D 00 29 68 0F A1 0F A1 ...Z..)h....
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 00 13 30 CB 07 09 66 40 22 89 C0 05 ..0...f@"...
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 42 20 D9 B . LRRP; Tgt=10600 Src=602
- +DMR slot1 BS DATA DCC=1 Idle
- Activity update: Slot1=No Activity Slot2=Indiv Data
- +DMR slot2 BS DATA DCC=1 Rate 1/2 Data 0A 2B 97 00 00 00 00 00 59 4C 08 B1 .+......YL..
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle ERR28
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- Sync:+DMR
- +DMR slot1 BS DATA DCC=1 Idle
- Null SLCO
- +DMR slot2 BS DATA DCC=1 Idle
- +DMR slot1 BS DATA DCC=1 Idle
- +DMR slot2 BS DATA DCC=1 Idle
- Sync: no sync
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