module top(hz100,reset,pb,ss7,ss6,ss5,ss4,ss3,ss2,ss1,ss0,left,right,red,green,blue);
    input hz100, reset;
    input [20:0] pb;
    output [7:0] ss7,ss6,ss5,ss4,ss3,ss2,ss1,ss0;
    output [7:0] left,right;
    output red,green,blue;

    wire[7:0] hz4, Q, Q2;
    wire[2:0] pos;

    count8du c(.CLK(Q2[4]), .M(pb[1]), .E(pb[2]), .AR(reset), .Q(Q));
    decode_led d0(.value(Q[3:0]), .ss(ss0), .enable(1'b1));
    decode_led d1(.value(Q[7:4]), .ss(ss1), .enable(1'b1));

    countn div(.CLK(hz100), .MAX(8'd24), .AR(reset), .E(1'b1), .Q(Q2));

    // NEXT PART
    // updown3 u(.AR(reset), .CLK(hz4[4]), .Q(pos));
    // display_ball disp(pos, ss0, ss1, ss2, ss3, ss4, ss5, ss6, ss7);

    // countn div(.CLK(hz100), .MAX(8'd24), .AR(reset), .E(1'b1), .Q(hz4));
endmodule

module display_ball(pos, ss0, ss1, ss2, ss3, ss4, ss5, ss6, ss7);
    input wire[2:0] pos;
    output wire[7:0] ss0, ss1, ss2, ss3, ss4, ss5, ss6, ss7;

    assign ss0 = (pos == 3'b000) ? 8'b01011100 : 8'b00000000;
    assign ss1 = (pos == 3'b001) ? 8'b01011100 : 8'b00000000;
    assign ss2 = (pos == 3'b010) ? 8'b01011100 : 8'b00000000;
    assign ss3 = (pos == 3'b011) ? 8'b01011100 : 8'b00000000;
    assign ss4 = (pos == 3'b100) ? 8'b01011100 : 8'b00000000;
    assign ss5 = (pos == 3'b101) ? 8'b01011100 : 8'b00000000;
    assign ss6 = (pos == 3'b110) ? 8'b01011100 : 8'b00000000;
    assign ss7 = (pos == 3'b111) ? 8'b01011100 : 8'b00000000;
endmodule

module updown3(AR, CLK, Q);
    input wire AR, CLK;
    output reg[2:0] Q;

    reg dir;
    reg next_dir;
    reg[2:0] nQ;

    always @ (Q) begin
        if (AR) begin
            Q <= 3'b000;
            dir <= 0;
        end
        else
            Q <= nQ;
            dir <= next_dir;
    end

    always @ (posedge CLK) begin
        if (dir == 1'b1) begin
            nQ[0] = ~Q[0];
            nQ[1] = Q[1] ^ (~Q[0]);
            nQ[2] = Q[2] ^ (~Q[0] & ~Q[1]);
            nQ[3] = Q[3] ^ (~Q[0] & ~Q[1] & ~Q[2]);
        end
        else begin
            nQ[0] = ~Q[0];
            nQ[1] = Q[1] ^ (Q[0]);
            nQ[2] = Q[2] ^ (Q[0] & Q[1]);
            nQ[3] = Q[3] ^ (Q[0] & Q[1] & Q[2]);
        end

        if (nQ == 3'd7)
            next_dir = 1;
        else if (nQ == 3'd0)
            next_dir = 0;
    end
endmodule

module countn(E, AR, CLK, Q, MAX);
    input wire E, AR, CLK;
    input wire[7:0] MAX;
    output wire[7:0] Q;

    wire r;
    assign r = AR | (MAX == Q);

    count8du c(.E(E), .M(1'b1), .AR(r), .CLK(CLK), .Q(Q));

endmodule

module count8du(E, M, AR, CLK, Q);
    input wire E, M, AR, CLK;
    output reg[7:0] Q;

    reg[7:0] nQ;

    always @ (posedge CLK or posedge AR) begin
        if (AR)
            Q <= 8'b00000000;
        else if (E) begin
            Q <= nQ;
        end
    end

    always @ (Q, M) begin
        if (M == 1'b0) begin
            nQ[0] = ~Q[0];
            nQ[1] = Q[1] ^ (~Q[0]);
            nQ[2] = Q[2] ^ (~Q[0] & ~Q[1]);
            nQ[3] = Q[3] ^ (~Q[0] & ~Q[1] & ~Q[2]);
            nQ[4] = Q[4] ^ (~Q[0] & ~Q[1] & ~Q[2] & ~Q[3]);
            nQ[5] = Q[5] ^ (~Q[0] & ~Q[1] & ~Q[2] & ~Q[3] & ~Q[4]);
            nQ[6] = Q[6] ^ (~Q[0] & ~Q[1] & ~Q[2] & ~Q[3] & ~Q[4] & ~Q[5]);
            nQ[7] = Q[7] ^ (~Q[0] & ~Q[1] & ~Q[2] & ~Q[3] & ~Q[4] & ~Q[5] & ~Q[6]);
        end
        else begin
            nQ[0] = ~Q[0];
            nQ[1] = Q[1] ^ (Q[0]);
            nQ[2] = Q[2] ^ (Q[0] & Q[1]);
            nQ[3] = Q[3] ^ (Q[0] & Q[1] & Q[2]);
            nQ[4] = Q[4] ^ (Q[0] & Q[1] & Q[2] & Q[3]);
            nQ[5] = Q[5] ^ (Q[0] & Q[1] & Q[2] & Q[3] & Q[4]);
            nQ[6] = Q[6] ^ (Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5]);
            nQ[7] = Q[7] ^ (Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5] & Q[6]);
        end
    end
endmodule

module decode_led(ss, value, enable);
    input wire[3:0] value;
    input wire enable;
    input wire[6:0] ss;

    assign ss[0] = (enable == 1) ? (~value[3] & ~value[2] & ~value[1] & ~value[0]) | (~value[3] & ~value[2] & value[1] & ~value[0]) | (~value[3] & ~value[2] & value[1] & value[0]) | (~value[3] & value[2] & ~value[1] & value[0]) | (~value[3] & value[2] & value[1] & ~value[0]) | (~value[3] & value[2] & value[1] & value[0]) | (value[3] & ~value[2] & ~value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & value[0]) | (value[3] & ~value[2] & value[1] & ~value[0]) | (value[3] & value[2] & ~value[1] & ~value[0]) | (value[3] & value[2] & value[1] & ~value[0]) | (value[3] & value[2] & value[1] & value[0]): 0;
    assign ss[1] = (enable == 1) ? (~value[3] & ~value[2] & ~value[1] & ~value[0]) | (~value[3] & ~value[2] & ~value[1] & value[0]) | (~value[3] & ~value[2] & value[1] & ~value[0]) | (~value[3] & ~value[2] & value[1] & value[0]) | (~value[3] & value[2] & ~value[1] & ~value[0]) | (~value[3] & value[2] & value[1] & value[0]) | (value[3] & ~value[2] & ~value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & value[0]) | (value[3] & ~value[2] & value[1] & ~value[0]) | (value[3] & value[2] & ~value[1] & value[0]): 0;
    assign ss[2] = (enable == 1) ? (~value[3] & ~value[2] & ~value[1] & ~value[0]) | (~value[3] & ~value[2] & ~value[1] & value[0]) | (~value[3] & ~value[2] & value[1] & value[0]) | (~value[3] & value[2] & ~value[1] & ~value[0]) | (~value[3] & value[2] & ~value[1] & value[0]) | (~value[3] & value[2] & value[1] & ~value[0]) | (~value[3] & value[2] & value[1] & value[0]) | (value[3] & ~value[2] & ~value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & value[0]) | (value[3] & ~value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & value[1] & value[0]) | (value[3] & value[2] & ~value[1] & value[0]): 0;
    assign ss[3] = (enable == 1) ? (~value[3] & ~value[2] & ~value[1] & ~value[0]) | (~value[3] & ~value[2] & value[1] & ~value[0]) | (~value[3] & ~value[2] & value[1] & value[0]) | (~value[3] & value[2] & ~value[1] & value[0]) | (~value[3] & value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & value[0]) | (value[3] & ~value[2] & value[1] & value[0]) | (value[3] & value[2] & ~value[1] & ~value[0]) | (value[3] & value[2] & ~value[1] & value[0]) | (value[3] & value[2] & value[1] & ~value[0]): 0;
    assign ss[4] = (enable == 1) ? (~value[3] & ~value[2] & ~value[1] & ~value[0]) | (~value[3] & ~value[2] & value[1] & ~value[0]) | (~value[3] & value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & ~value[0]) | (value[3] & ~value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & value[1] & value[0]) | (value[3] & value[2] & ~value[1] & ~value[0]) | (value[3] & value[2] & ~value[1] & value[0]) | (value[3] & value[2] & value[1] & ~value[0]) | (value[3] & value[2] & value[1] & value[0]): 0;
    assign ss[5] = (enable == 1) ? (~value[3] & ~value[2] & ~value[1] & ~value[0]) | (~value[3] & value[2] & ~value[1] & ~value[0]) | (~value[3] & value[2] & ~value[1] & value[0]) | (~value[3] & value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & value[0]) | (value[3] & ~value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & value[1] & value[0]) | (value[3] & value[2] & ~value[1] & ~value[0]) | (value[3] & value[2] & value[1] & ~value[0]) | (value[3] & value[2] & value[1] & value[0]): 0;
    assign ss[6] = (enable == 1) ? (~value[3] & ~value[2] & value[1] & ~value[0]) | (~value[3] & ~value[2] & value[1] & value[0]) | (~value[3] & value[2] & ~value[1] & ~value[0]) | (~value[3] & value[2] & ~value[1] & value[0]) | (~value[3] & value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & ~value[0]) | (value[3] & ~value[2] & ~value[1] & value[0]) | (value[3] & ~value[2] & value[1] & ~value[0]) | (value[3] & ~value[2] & value[1] & value[0]) | (value[3] & value[2] & ~value[1] & value[0]) | (value[3] & value[2] & value[1] & ~value[0]) | (value[3] & value[2] & value[1] & value[0]): 0;
endmodule