CML devicetree

chip soc/intel/cannonlake
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
	}"

        # Send an extra VR mailbox command for the PS4 exit issue
        register "SendVrMbxCmd" = "2"

# CPU (soc/intel/cannonlake/cpu.c)
	# Power limit
	register "power_limits_config" = "{
		.tdp_pl1_override = 20,
		.tdp_pl2_override = 30,
	}"

	# Enable Enhanced Intel SpeedStep
	register "eist_enable" = "1"

# Graphics (soc/intel/cannonlake/graphics.c)
	# IGD Displays
	register "gfx" = "GMA_STATIC_DISPLAYS(0)"

# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
	# FSP configuration
	register "SaGv" = "SaGv_Enabled"
	register "ScsEmmcHs400Enabled" = "1"

# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
	# Serial I/O
	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
		[PchSerialIoIndexSPI0] = PchSerialIoPci,
		[PchSerialIoIndexSPI1] = PchSerialIoPci,
		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
	}"

	# Misc
	register "AcousticNoiseMitigation" = "1"
	register "satapwroptimize" = "1"

	# Power
	register "PchPmSlpS3MinAssert" = "3"		# 50ms
	register "PchPmSlpS4MinAssert" = "1"		# 1s
	register "PchPmSlpSusMinAssert" = "2"		# 500ms
	register "PchPmSlpAMinAssert" = "4"		# 2s

	# Thermal
	register "tcc_offset" = "12"

	# Enable eDP device
	register "DdiPortEdp" = "1"

	# Enable HPD for DDI ports B/C
	register "DdiPortBHpd" = "1"
	register "DdiPortCHpd" = "1"

	# Enable DDC for DDI ports B/C
	register "DdiPortBDdc" = "1"
	register "DdiPortCDdc" = "1"

	# Disable S0ix
	register "s0ix_enable" = "0"

# PM Util (soc/intel/cannonlake/pmutil.c)
	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
	register "gpe0_dw0" = "PMC_GPP_B"
	register "gpe0_dw1" = "PMC_GPP_C"
	register "gpe0_dw2" = "PMC_GPP_E"

# Actual device tree.
	device cpu_cluster 0 on
		device lapic 0 on end
	end

	device domain 0 on
		device pci 00.0 on  end 			# Host Bridge
		device pci 02.0 on  end 			# Integrated Graphics Device
		device pci 04.0 on 				# SA Thermal Device
			register "Device4Enable" = "1"
		end
		device pci 08.0 on  end 			# Gaussian Mixture Model
		device pci 12.0 on  end 			# Thermal Subsystem
		device pci 12.5 off end 			# UFS SCS
		device pci 12.6 off end 			# GSPI #2
		device pci 14.0 on	 			# USB xHCI
			# USB2
			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C port 1
			register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-A port 2
			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# uSD Card
			register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"		# Type-A port 3
			register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"		# Camera
			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Actual Bluetooth port

			# USB3
			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
		end
		device pci 14.1 off end 			# USB xDCI (OTG)
		device pci 14.3 on				# CNVi wifi
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end
		device pci 14.5 off end				# SDCard
		device pci 15.0 on				# I2C #0
			chip drivers/i2c/hid
				register "generic.hid" = ""PCT1336""
				register "generic.desc" = ""Touchpad""
				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
				register "generic.probed" = "1"
				register "hid_desc_reg_offset" = "0x20"
				device i2c 2c on end
			end
		end
	        device pci 15.1 on  end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 16.0 off end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off end # Management Engine Interface 3
		device pci 16.5 off end # Management Engine Interface 4
		device pci 17.0 on	 			# SATA
			register "SataSalpSupport" = "1"

			# Port 1
			register "SataPortsEnable[1]" = "1"
			register "SataPortsDevSlp[1]" = "0"

			# Port 2
			register "SataPortsEnable[2]" = "1"
			register "SataPortsDevSlp[2]" = "0"
		end
		device pci 19.0 off end 			# I2C #4
		device pci 19.1 off end 			# I2C #5
		device pci 19.2 on  end 			# UART #2
		device pci 1a.0 on  end 			# eMMC - not fitted
                device pci 1c.0 off end 			# PCI Express Port 1
                device pci 1c.1 off end 			# PCI Express Port 2
                device pci 1c.2 off end 			# PCI Express Port 3
                device pci 1c.3 off end				# PCI Express Port 4
                device pci 1c.4 off end 			# PCI Express Port 5
                device pci 1c.5 off end 			# PCI Express Port 6
                device pci 1c.6 off end 			# PCI Express Port 7
                device pci 1c.7 off end 			# PCI Express Port 8
                device pci 1d.0 on				# PCI Express Port 9  (SSD x4)
			device pci 00.0 on end
			register "PcieRpSlotImplemented[8]" = "1"
			register "PcieRpEnable[8]" = "1"
                        register "PcieRpLtrEnable[8]" = "1"
			register "PcieClkSrcUsage[1]" = "8"
			register "PcieClkSrcClkReq[1]" = "1"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
		end
                device pci 1d.1 off end 			# PCI Express Port 10
                device pci 1d.2 off end 			# PCI Express Port 11
                device pci 1d.3 off end 			# PCI Express Port 12
                device pci 1d.4 on	 			# PCI Express Port 13 (LAN)
			device pci 00.0 on end
			register "PcieRpSlotImplemented[12]" = "1"
			register "PcieRpEnable[12]" = "0"
			register "PcieRpLtrEnable[12]" = "0"
			register "PcieClkSrcUsage[2]" = "12"
			register "PcieClkSrcClkReq[2]" = "2"
		end
                device pci 1d.5 on				# PCI Express Port 14 (WLAN)
			register "PcieRpSlotImplemented[13]" = "1"
		        register "PcieRpEnable[13]" = "1"
			register "PcieRpLtrEnable[13]" = "1"
			register "PcieClkSrcUsage[0]" = "13"
			register "PcieClkSrcClkReq[0]" = "0"
			chip drivers/wifi/generic
				device pci 00.0 on end
			end
		end
                device pci 1d.6 off end # PCI Express Port 15
                device pci 1d.7 off end # PCI Express Port 16
		device pci 1e.0 on  end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 off end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1f.0 on				# LPC Interface
			# LPC configuration from lspci -s 1f.0 -xxx
			# Address 0x84: Decode 0x680 - 0x68F
			register "gen1_dec" = "0x000c0681"
			# Address 0x88: Decode
			register "gen2_dec" = "0x000c1641"
			# Address 0x8C: Decode 0x200 - 0x2FF
			register "gen3_dec" = "0x00fc0201"
			# Address 0x90: Decode 0x80 - 0x8F (Port 80)
			register "gen4_dec" = "0x000c0081"

			chip ec/starlabs/it8987
				# Port 4Eh/4Fh
				device pnp 4e.0 on		# IO Interface
				end
                                device pnp 4e.5 off end         # KBC Mouse
                                device pnp 4e.6 on              # KBC Keyboard
                                        io  0x60 = 0x0060
                                        io  0x62 = 0x0064
                                        irq 0x70 = 1
                                end
			end
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end
		device pci 1f.1 off end 			# P2SB
		device pci 1f.2 off end 			# Power Management Controller
		device pci 1f.3 on				# Intel HDA
			subsystemid 0x10ec 0x119e
			register "PchHdaAudioLinkHda" = "1"
		end
		device pci 1f.4 on  end 			# SMBus
		device pci 1f.5 on  end 			# PCH SPI
		device pci 1f.6 off end 			# GbE
	end
end