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- module register(
- clk,
- rst,
- oe,
- we,
- in,
- out,
- disp_out
- );
- parameter width = 16;
- input clk;
- input rst;
- input oe;
- input we;
- input [width-1 : 0] in;
- output[width-1 : 0] out;
- output[width-1 : 0] disp_out;
- reg [width-1 : 0] data;
- always @(posedge clk) begin
- if(rst)
- data <= 0;
- else if(we)
- data <= in;
- end
- assign out = oe ? data : 0;
- assign disp_out = data;
- endmodule
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